參數(shù)資料
型號(hào): M48T18-100PC1
廠商: STMICROELECTRONICS
元件分類: 時(shí)鐘/數(shù)據(jù)恢復(fù)及定時(shí)提取
英文描述: 0 TIMER(S), REAL TIME CLOCK, PDIP28
封裝: 0.600 INCH, ROHS COMPLIANT, PLASTIC, PCDIP-28
文件頁(yè)數(shù): 2/31頁(yè)
文件大?。?/td> 256K
代理商: M48T18-100PC1
Operation modes
M48T08, M48T08Y, M48T18
Table 3.
Read mode AC characteristics
Note:
Valid for ambient operating temperature: TA = 0 to 70°C; VCC = 4.75 to 5.5 V or 4.5 to 5.5 V
(except where noted).
2.2
Write mode
The M48T08/18/08Y is in the WRITE mode whenever W, E1, and E2 are active. The start of
a WRITE is referenced from the latter occurring falling edge of W or E1, or the rising edge of
E2. A WRITE is terminated by the earlier rising edge of W or E1, or the falling edge of E2.
The addresses must be held valid throughout the cycle. E1 or W must return high or E2 low
for a minimum of tE1HAX or tE2LAX from chip enable or tWHAX from WRITE enable prior to the
initiation of another READ or WRITE cycle. Data-in must be valid tDVWH prior to the end of
WRITE and remain valid for tWHDX afterward. G should be kept high during WRITE cycles to
avoid bus contention; however, if the output bus has been activated by a low on E1 and G
and a high on E2, a low on W will disable the outputs tWLQZ after W falls.
Symbol
Parameter(1)
M48T08/M48T18/T08Y
Unit
–100/–10 (T08Y)
–150/–15 (T08Y)
Min
Max
Min
Max
tAVAV
READ cycle time
100
150
ns
tAVQV
Address valid to output valid
100
150
ns
tE1LQV
Chip enable 1 low to output valid
100
150
ns
tE2HQV
Chip enable 2 high to output valid
100
150
ns
tGLQV
Output enable low to output valid
50
75
ns
tE1LQX
Chip enable 1 low to output transition
10
ns
tE2HQX
Chip enable 2 high to output transition
10
ns
tGLQX
Output enable low to output transition
5
ns
tE1HQZ
Chip enable 1 high to output Hi-Z
50
75
ns
tE2LQZ
Chip enable 2 low to output Hi-Z
50
75
ns
tGHQZ
Output enable high to output Hi-Z
40
60
ns
tAXQX
Address transition to output transition
5
ns
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