參數(shù)資料
型號(hào): M48T02-150PC1
廠商: STMICROELECTRONICS
元件分類: 時(shí)鐘/數(shù)據(jù)恢復(fù)及定時(shí)提取
英文描述: 0 TIMER(S), REAL TIME CLOCK, PDIP24
封裝: 0.600 INCH, ROHS COMPLIANT, PLASTIC, DIP-24
文件頁(yè)數(shù): 4/25頁(yè)
文件大?。?/td> 199K
代理商: M48T02-150PC1
Clock operations
M48T02, M48T12
3
Clock operations
3.1
Reading the clock
Updates to the TIMEKEEPER registers should be halted before clock data is read to
prevent reading data in transition. The BiPORT TIMEKEEPER cells in the RAM array are
only data registers and not the actual clock counters, so updating the registers can be halted
without disturbing the clock itself.
Updating is halted when a '1' is written to the READ bit, the seventh bit in the control
register. As long as a '1' remains in that position, updating is halted. After a halt is issued,
the registers reflect the count; that is, the day, date, and the time that were current at the
moment the halt command was issued.
All of the TIMEKEEPER registers are updated simultaneously. A halt will not interrupt an
update in progress. Updating is within a second after the bit is reset to a '0.'
3.2
Setting the clock
The eighth bit of the control register is the WRITE bit. Setting the WRITE bit to a '1,' like the
READ bit, halts updates to the TIMEKEEPER registers. The user can then load them with
the correct day, date, and time data in 24-hour BCD format (on Table5 on page13).
Resetting the WRITE bit to a '0' then transfers the values of all time registers (7F9-7FF) to
the actual TIMEKEEPER counters and allows normal operation to resume. The FT bit and
the bits marked as '0' in Table 5 on page 13 must be written to '0' to allow for normal
TIMEKEEPER and RAM operation.
See the application note AN923, “TIMEKEEPER rolling into the 21st century” for
information on century rollover.
相關(guān)PDF資料
PDF描述
M48T18-100MH1TR 0 TIMER(S), REAL TIME CLOCK, PDSO28
M48T18-100MH1 0 TIMER(S), REAL TIME CLOCK, PDSO28
M48T18-150PC1 0 TIMER(S), REAL TIME CLOCK, PDIP28
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