參數(shù)資料
型號: M470L3223DT0-CB0
廠商: SAMSUNG SEMICONDUCTOR CO. LTD.
英文描述: 256MB DDR SDRAM MODULE
中文描述: 256MB的DDR內存模塊
文件頁數(shù): 7/16頁
文件大?。?/td> 171K
代理商: M470L3223DT0-CB0
M470L3223DT0
Rev. 0.0 Dec. 2001
DDR SDRAM I
DD
spec table
* Module
I
DD
was calculated on the basis of component
I
DD
and can be differently measured according to DQ loading cap.
Symbol
B3(DDR333@CL=2.5)B0(DDR266@CL=2.5)
640
880
24
160
144
240
360
1120
1120
1320
24
12
2240
A0(DDR200@CL=2)
Unit
Notes
IDD0
IDD1
IDD2P
IDD2F
IDD2Q
IDD3P
IDD3N
IDD4R
IDD4W
IDD5
720
960
24
200
160
280
440
1360
1360
1440
24
12
2600
600
800
24
144
128
200
320
960
920
1200
24
12
1880
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
mA
IDD6
Normal
Low power
IDD7A
Optional
< Detailed test conditions for DDR SDRAM IDD1 & IDD7A >
IDD1 : Operating current: One bank operation
1. Only one bank is accessed with tRC(min), Burst Mode, Address and Control inputs on NOP edge are changing once
per clock cycle. lout = 0mA
2. Timing patterns
- DDR200(100Mhz, CL=2) : tCK = 10ns, CL2, BL=4, tRCD = 2*tCK, tRAS = 5*tCK
Read : A0 N R0 N N P0 N A0 N - repeat the same timing with random address changing
*50% of data changing at every burst
- DDR266B(133Mhz, CL=2.5) : tCK = 7.5ns, CL=2.5, BL=4, tRCD = 3*tCK, tRC = 9*tCK, tRAS = 5*tCK
Read : A0 N N R0 N P0 N N N A0 N - repeat the same timing with random address changing
*50% of data changing at every burst
- DDR266A (133Mhz, CL=2) : tCK = 7.5ns, CL=2, BL=4, tRCD = 3*tCK, tRC = 9*tCK, tRAS = 5*tCK
Read : A0 N N R0 N P0 N N N A0 N - repeat the same timing with random address changing
*50% of data changing at every burst
- DDR333(166Mhz, CL=2.5) : tCK=6ns, CL=2.5, BL=4, tRCD=10*tCK, tRAS=7*tCK
Read : A0 N N R0 N P0 N N N A0 N - repeat the same timing with random address changing
*50% of data changing at every burst
Legend : A=Activate, R=Read, W=Write, P=Precharge, N=NOP
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