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參數(shù)資料
| 型號(hào)： | M464S6453CKS |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | PC133/PC100 SODIMM |
| 中文描述： | PC133/PC100的SODIMM |
| 文件頁(yè)數(shù)： | 11/12頁(yè) |
| 文件大?。?/td> | 80K |
| 代理商： | M464S6453CKS |
M464S6453CKS
Rev. 0.1 Feb. 2002
PC133/PC100 SODIMM
Byte
#
Function described
Function Supported
Hex value
Note
-7A
-1H
-1L
-7A
-1H
-1L
0
# of bytes written into serial memory at module manufacturer
128bytes
80h
1
Total # of bytes of SPD memory device
256bytes (2K-bit)
08h
2
Fundamental memory type
SDRAM
04h
3
# of row address on this assembly
13
0Dh
1
4
# of column address on this assembly
10
0Ah
1
5
# of module Rows on this assembly
2 Rows
02h
6
Data width of this assembly
64 bits
40h
7
...... Data width of this assembly
-
00h
8
Voltage interface standard of this assembly
LVTTL
01h
9
SDRAM cycle time from clock @CAS latency of 3
7.5ns
10ns
10ns
75h
A0h
A0h
2
10
SDRAM access time from clock @CAS latency of 3
5.4ns
6ns
6ns
54h
60h
60h
2
11
DIMM configuration type
Non parity
00h
12
Refresh rate & type
7.8us, support self refresh
82h
13
Primary SDRAM width
x8
08h
14
Error checking SDRAM width
None
00h
15
Minimum clock delay for back-to-back random column address
t
CCD
= 1CLK
01h
16
SDRAM device attributes : Burst lengths supported
1, 2, 4, 8 & full page
8Fh
17
SDRAM device attributes : # of banks on SDRAM device
4 banks
04h
18
SDRAM device attributes : CAS latency
2&3
06h
19
SDRAM device attributes : CS latency
0 CLK
01h
20
SDRAM device attributes : Write latency
0 CLK
01h
21
SDRAM module attributes
Non-buffered/Non-Regis-
tered & redundant addressing
00h
22
SDRAM device attributes : General
+/- 10% voltage toleance,
Burst Read Single bit Write
precharge all, auto precharge
0Eh
23
SDRAM cycle time @CAS latency of 2
10ns
10ns
12ns
A0h
A0h
C0h
2
24
SDRAM access time @CAS latency of 2
6ns
6ns
7ns
60h
60h
70h
2
25
SDRAM cycle time @CAS latency of 1
-
00h
2
26
SDRAM access time @CAS latency of 1
-
00h
2
27
Minimum row precharge time (=t
RP
)
20ns
14h
28
Minimum row active to row active delay (t
RRD
)
15ns
20ns
20ns
0Fh
14h
14h
29
Minimum RAS to CAS delay (=t
RCD
)
20ns
14h
30
Minimum activate precharge time (=t
RAS
)
45ns
50ns
50ns
2Dh
32ns
32ns
31
Module Row density
2 Rows of 256MB
40h
32
Command and Address signal input setup time
1.5ns
2ns
2ns
15h
20h
20h
33
Command and Address signal input hold time
0.8ns
1ns
1ns
08h
10h
10h
34
Data signal input setup time
1.5ns
2ns
2ns
15h
20h
20h
M464S6453CKS-L7A/L1H/L1L, C7A/C1H/C1L(Intel SPD 1.2B ver. based)
Organization : 64MX64
Composition : 64MX8 *8
Used component part # : K4S510832C-L7A/C7A/L1H/C1H/L1L/C1L
# of rows in module : 2 rows
# of banks in component : 4 banks
Feature : 1,200 mil height & double sided
Refresh : 8K/64ms
Contents
:
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| M464S6453EN0-C7A | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:SDRAM Unbuffered SODIMM |
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| M464S6554BTS | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:SDRAM Unbuffered SODIMM |
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