參數(shù)資料
型號(hào): M41ST85Y-85MH6
廠商: STMICROELECTRONICS
元件分類: 時(shí)鐘/數(shù)據(jù)恢復(fù)及定時(shí)提取
英文描述: 1 TIMER(S), REAL TIME CLOCK, PDSO28
封裝: 0.330 INCH, SNAPHAT, PLASTIC, SOH-28
文件頁(yè)數(shù): 9/32頁(yè)
文件大?。?/td> 171K
代理商: M41ST85Y-85MH6
17/32
M41ST85Y, M41ST85W
Figure 15. Alarm Interrupt Reset Waveforms
Table 4. Alarm Repeat Modes
Watchdog Timer
The watchdog timer can be used to detect an out-
of-control microprocessor. The user programs the
watchdog timer by setting the desired amount of
time-out into the Watchdog Register, address 09h.
Bits BMB4-BMB0 store a binary multiplier and the
two lower order bits RB1-RB0 select the resolu-
tion, where 00=1/16 second, 01=1/4 second, 10=1
second, and 11=4 seconds. The amount of time-
out is then determined to be the multiplication of
the five bit multiplier value with the resolution. (For
example: writing 00001110 in the Watchdog Reg-
ister = 3*1 or 3 seconds). If the processor does not
reset the timer within the specified period, the
M41ST85Y/W sets the WDF (Watchdog Flag) and
generates a watchdog interrupt or a microproces-
sor reset.
Note: If the Square Wave function is enabled, the
accuracy of the Watchdog Timer will be a function
of the selected resolution.
The most significant bit of the Watchdog Register
is the Watchdog Steering Bit (WDS). When set to
a ‘0’, the watchdog will activate the IRQ/FT/OUT
pin when timed-out. When WDS is set to a ‘1’, the
watchdog will output a negative pulse on the RST
pin for tREC. The Watchdog register, FT, AFE, ABE
and SQWE Bits will reset to a ‘0’ at the end of a
Watchdog time-out when the WDS bit is set to a
‘1’.
The watchdog timer can be reset by two methods:
1) a transition (high-to-low or low-to-high) can be
applied to the Watchdog Input pin (WDI) or 2) the
microprocessor can perform a write of the Watch-
dog Register. The time-out period then starts over.
Note: The WDI pin should be tied to VSS if not
used.
In order to perform a software reset of the watch-
dog timer, the original time-out period can be writ-
ten into the Watchdog
Register, effectively
restarting the count-down cycle.
Should the watchdog timer time-out, and the WDS
bit is programmed to output an interrupt, a value of
00h needs to be written to the Watchdog Register
in order to clear the IRQ/FT/OUT pin. This will also
disable the watchdog function until it is again pro-
grammed correctly. A read of the Flags Register
will reset the Watchdog Flag (Bit D7; Register
0Fh).
The watchdog function is automatically disabled
upon power-up and the Watchdog Register is
cleared. If the watchdog function is set to output to
the IRQ/FT/OUT pin and the frequency test func-
tion is activated, the watchdog function prevails
and the frequency test function is denied. The
OUT function has the lowest priority and will only
be enabled when the Watchdog Register (09h),
AFE Bit and FT Bit are ‘0.’
RPT5
RPT4
RPT3
RPT2
RPT1
Alarm Setting
11111
Once per Second
11110
Once per Minute
11100
Once per Hour
11000
Once per Day
10000
Once per Month
00000
Once per Year
AI03664
IRQ/FT/OUT
ACTIVE FLAG
0Fh
0Eh
10h
HIGH-Z
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