參數(shù)資料
型號(hào)： M41ST84YMH6E
廠商： STMICROELECTRONICS
元件分類： 時(shí)鐘/數(shù)據(jù)恢復(fù)及定時(shí)提取
英文描述： 1 TIMER(S), REAL TIME CLOCK, PDSO28
封裝： 0.330 INCH, LEAD FREE, PLASTIC, SOH-28
文件頁(yè)數(shù)： 3/31頁(yè)
文件大?。?/td> 507K
代理商： M41ST84YMH6E
11/31
M41ST84Y, M41ST84W
Figure 13. Alternate READ Mode Sequence
WRITE Mode
In this mode the master transmitter transmits to
the M41ST84Y/W slave receiver. Bus protocol is
shown in Figure 14., page 11. Following the
START condition and slave address, a logic '0' (R/
W=0) is placed on the bus and indicates to the ad-
dressed device that word address An will follow
and is to be written to the on-chip address pointer.
The data word to be written to the memory is
strobed in next and the internal address pointer is
incremented to the next memory location within
the RAM on the reception of an acknowledge
clock. The M41ST84Y/W slave receiver will send
an acknowledge clock to the master transmitter af-
ter it has received the slave address (see Figure
11., page 10) and again after it has received the
word address and each data byte.
Data Retention Mode
With valid VCC applied, the M41ST84Y/W can be
accessed as described above with READ or
WRITE cycles. Should the supply voltage decay,
the M41ST84Y/W will automatically deselect,
write protecting itself when VCC falls between
VPFD(max) and VPFD(min). This is accomplished
by internally inhibiting access to the clock regis-
ters. At this time, the Reset pin (RST) is driven ac-
tive and will remain active until VCC returns to
nominal levels. When VCC falls below the Battery
Back-up Switchover Voltage (VSO), power input is
switched from the VCC pin to the SNAPHAT
(or
external) battery, and the clock registers and
SRAM are maintained from the attached battery
supply.
All outputs become high impedance. On power up,
when VCC returns to a nominal value, write protec-
tion continues for tREC. The RST signal also re-
mains
active
during
this
time
(see
For a further more detailed review of lifetime calcu-
lations, please see Application Note AN1012.
Figure 14. WRITE Mode Sequence
AI00895
BUS ACTIVITY:
ACK
S
ACK
NO
ACK
STOP
START
P
SDA LINE
BUS ACTIVITY:
MASTER
R/W
DATA n
DATA n+1
DATA n+X
SLAVE
ADDRESS
AI00591
BUS ACTIVITY:
ACK
S
ACK
STOP
START
P
SDA LINE
BUS ACTIVITY:
MASTER
R/W
DATA n
DATA n+1
DATA n+X
WORD
ADDRESS (An)
SLAVE
ADDRESS
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