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參數資料
| 型號： | M4-192/96-12VI |
| 廠商： | LATTICE SEMICONDUCTOR CORP |
| 元件分類： | PLD |
| 英文描述： | High Performance E 2 CMOS In-System Programmable Logic |
| 中文描述： | EE PLD, 12 ns, PQFP144 |
| 封裝： | TQFP-144 |
| 文件頁數： | 4/46頁 |
| 文件大?。?/td> | 754K |
| 代理商： | M4-192/96-12VI |
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12
MACH 4 Family
Note:
1. Polarity of CLK/LE can be programmed
Although the macrocell shows only one input to the register, the XOR gate in the logic allocator
allows the D-, T-type register to emulate J-K, and S-R behavior. In this case, the available product
terms are divided between J and K (or S and R). When congured as J-K, S-R, or T-type, the
extra product term must be used on the XOR gate input for ip-op emulation. In any register
type, the polarity of the inputs can be programmed.
The clock input to the ip-op can select any of the four PAL block clocks in synchronous mode,
with the additional choice of either polarity of an individual product term clock in the
asynchronous mode.
The initialization circuit depends on the mode. In synchronous mode (Figure 7), asynchronous
reset and preset are provided, each driven by a product term common to the entire PAL block.
Table 8. Register/Latch Operation
Conguration
Input(s)
CLK/LE 1
Q+
D-type Register
D=X
D=0
D=1
0,1, ↓ (↑)
↑ (↓)
Q
0
1
T-type Register
T=X
T=0
T=1
0, 1, ↓ (↑)
↑ (↓)
Q
D-type Latch
D=X
D=0
D=1
1(0)
0(1)
Q
0
1
Power-Up
Reset
AP
D/T/L
AR
Q
PAL-Block
Initialization
Product Terms
a. Power-up reset
Power-Up
Preset
AP
D/L
PAL-Block
Initialization
Product Terms
AR
Q
17466G-012
17466G-013
Figure 7. Synchronous Mode Initialization Congurations
b. Power-up preset
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