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參數(shù)資料
| 型號(hào)： | M391T2953BG0-CC |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | TVS UNIDIRECT 1500W 160V SMC |
| 中文描述： | 無緩沖DDR2的內(nèi)存模塊 |
| 文件頁數(shù)： | 18/23頁 |
| 文件大?。?/td> | 367K |
| 代理商： | M391T2953BG0-CC |
Rev. 1.2 Jan. 2005
256MB,512MB,1GB Unbuffered DIMMs
DDR2 SDRAM
Parameter
Symbol
DDR2-533
DDR2-400
Units
Notes
min
max
min
max
Control & Address input
pulse width for each input
tIPW
0.6
x
0.6
x
tCK
DQ and DM input pulse
width for each input
tDIPW
0.35
x
0.35
x
tCK
Data-out high-impedance
time from CK/CK
tHZ
x
tAC max
x
tAC max
ps
DQS low-impedance time
from CK/CK
tLZ(DQS)
tAC min
tAC max
tAC min
tAC max
ps
DQ low-impedance time
from CK/CK
tLZ(DQ)
2* tACmin
tAC max
2* tACmin
tAC max
ps
DQS-DQ skew for DQS and
associated DQ signals
tDQSQ
x
300
x
350
ps
DQ hold skew factor
tQHS
x
400
x
450
ps
DQ/DQS output hold time
from DQS
tQH
tHP - tQHS
x
tHP - tQHS
x
ps
Write command to first DQS
latching transition
tDQSS
WL-0.25
WL+0.25
WL-0.25
WL+0.25
tCK
DQS input high pulse width
tDQSH
0.35
x
0.35
x
tCK
DQS input low pulse width
tDQSL
0.35
x
0.35
x
tCK
DQS falling edge to CK
setup time
tDSS
0.2
x
0.2
x
tCK
DQS falling edge hold time from
CK
tDSH
0.2
x
0.2
x
tCK
Mode register set command
cycle time
tMRD
2
x
2
x
tCK
Write postamble
tWPST
0.4
0.6
0.4
0.6
tCK
Write preamble
tWPRE
0.35
x
0.35
x
tCK
Address and control input
hold time
tIH
375
x
475
x
ps
Address and control input
setup time
tIS
250
x
350
x
ps
Read preamble
tRPRE
0.9
1.1
0.9
1.1
tCK
Read postamble
tRPST
0.4
0.6
0.4
0.6
tCK
Active to active command
period for 1KB page size
products
tRRD
7.5
x
7.5
x
ns
Active to active command
period for
2KB page size
products
tRRD
10
x
10
x
ns
Four Activate Window for
1KB page size products
tFAW
37.5
37.5
ns
Four Activate Window for
2KB page size products
tFAW
50
50
ns
CAS to CAS command
delay
tCCD
2
2
tCK
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