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參數(shù)資料
| 型號： | M390S3323DT1-C7A |
| 元件分類： | DRAM |
| 英文描述： | 32M X 72 SYNCHRONOUS DRAM MODULE, 5.4 ns, DMA168 |
| 封裝： | DIMM-168 |
| 文件頁數(shù)： | 12/12頁 |
| 文件大?。?/td> | 108K |
| 代理商： | M390S3323DT1-C7A |
M390S3323DT1
PC133 Registered DIMM
Rev. 0.1 Sept. 2001
SIMPLIFIED TRUTH TABLE
(V=Valid, X=Don
′t care, H=Logic high, L=Logic low)
Command
CKEn-1
CKEn
CS
RAS
CAS
WE
DQM
BA0,1
A10 /AP
A11
A9 ~ A 0
Note
Register
Mode register set
H
X
L
X
OP code
1,2
Refresh
Auto refresh
H
L
H
X
3
Self
refresh
Entry
L
3
Exit
L
H
L
H
X
3
H
X
3
Bank active & row addr.
H
X
L
H
X
V
Row address
Read &
column address
Auto precharge disable
H
X
L
H
L
H
X
V
L
Column
address
(A0 ~ A9)
4
Auto precharge enable
H
4,5
Write &
column address
Auto precharge disable
H
X
L
H
L
X
V
L
Column
address
(A0 ~ A 9)
4
Auto precharge enable
H
4,5
Burst stop
H
X
L
H
L
X
6
Precharge
Bank selection
H
X
L
H
L
X
V
L
X
All banks
X
H
Clock suspend or
active power down
Entry
H
L
H
X
L
V
Exit
L
H
X
Precharge power down mode
Entry
H
L
H
X
L
H
Exit
L
H
X
L
V
DQM
H
V
X
7
No operation command
H
X
H
X
L
H
1. OP Code : Operand code
A0 ~ A11 & BA0 ~ BA1 : Program keys. (@ MRS)
2. MRS can be issued only at all banks precharge state.
A new command can be issued after 2 clock cycles of MRS.
3. Auto refresh functions are as same as CBR refresh of DRAM.
The automatical precharge without row precharge command is meant by "Auto".
Auto/self refresh can be issued only at all banks precharge state.
4. BA 0 ~ BA1 : Bank select addresses.
If both BA0 and BA1 are "Low" at read, write, row active and precharge, bank A is selected.
If both BA0 is "Low" and BA 1 is "High" at read, write, row active and precharge, bank B is selected.
If both BA0 is "High" and BA1 is "Low" at read, write, row active and precharge, bank C is selected.
If both BA0 and BA1 are "High" at read, write, row active and precharge, bank D is selected.
If A10/AP is "High" at row precharge, BA0 and BA1 is ignored and all banks are selected.
5. During burst read or write with auto precharge, new read/write command can not be issued.
Another bank read/write command can be issued after the end of burst.
New row active of the associated bank can be issued at t RP after the end of burst.
6. Burst stop command is valid at every burst length.
7. DQM sampled at positive going edge of a CLK and masks the data-in at the very CLK (Write DQM latency is 0),
but makes Hi-Z state the data-out of 2 CLK cycles after. (Read DQM latency is 2)
Notes :
X
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相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M390S6450CT1 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:64Mx72 SDRAM DIMM with PLL & Register based on 64Mx4, 4Banks, 8K Ref., 3.3V Synchronous DRAMs with SPD |
| M390S6450CT1-C7A | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:64Mx72 SDRAM DIMM with PLL & Register based on 64Mx4, 4Banks, 8K Ref., 3.3V Synchronous DRAMs with SPD |
| M390S6450CT1-C7C | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:64Mx72 SDRAM DIMM with PLL & Register based on 64Mx4, 4Banks, 8K Ref., 3.3V Synchronous DRAMs with SPD |
| M390S6450ET1-C7A | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:168pin Registered Module based on 256Mb E-die with 72-bit ECC |
| M390S6450ET1-C7A00 | 制造商:Samsung 功能描述:256 SDRAM MODULE X72 TSOP2-400 - Trays |
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