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參數(shù)資料
| 型號： | M390S2858CTU-C7A |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | PC133/PC100 Low Profile Registered DIMM |
| 中文描述： | PC133/PC100內(nèi)存超薄注冊 |
| 文件頁數(shù)： | 11/12頁 |
| 文件大?。?/td> | 244K |
| 代理商： | M390S2858CTU-C7A |
M390S2858CTU
Rev. 0.1 Sept. 2001
PC133/PC100 Low Profile Registered DIMM
M390S2858CTU-C7C/C7A/C1H/C1L
Organization : 128MX72
Composition : 128MX4 * 18ea
Used component part # : K4S510632C
# of banks in module : 2 Rows
# of banks in component : 4 banks
Feature : 1,200 mil height & double sided
Refresh : 8K/64ms
Contents
:
Byte #
Function described
Function Supported
Hex value
Note
-7C
-7A
-1H
-1L
-7C
-7A
-1H
-1L
0
# of bytes written into serial memory at module manufacturer
128bytes
80h
1
Total # of bytes of SPD memory device
256bytes (2K-bit)
08h
2
Fundamental memory type
SDRAM
04h
3
# of row address on this assembly
13
0Dh
1
4
# of column address on this assembly
11
0Bh
1
5
# of module Rows on this assembly
2
row
02h
6
Data width of this assembly
72 bits
48h
7
...... Data width of this assembly
-
00h
8
Voltage interface standard of this assembly
LVTTL
01h
9
SDRAM cycle time from clock @CAS latency of 3
7.5ns
10ns
10ns
10ns
75h
75h
A0h
A0h
2
10
SDRAM access time from clock @CAS latency of 3
5.4ns
6ns
6ns
6ns
54h
54h
60h
60h
2
11
DIMM configuration type
ECC
02h
12
Refresh rate & type
7.8us, support self refresh
82h
13
Primary SDRAM width
x4
04h
14
Error checking SDRAM width
x4
04h
15
Minimum clock delay for back-to-back random column address
t
CCD
= 1CLK
01h
16
SDRAM device attributes : Burst lengths supported
1, 2, 4, 8 & full page
8Fh
17
SDRAM device attributes : # of banks on SDRAM device
4 banks
04h
18
SDRAM device attributes : CAS latency
2 & 3
06h
19
SDRAM device attributes : CS latency
0 CLK
01h
20
SDRAM device attributes : Write latency
0 CLK
01h
21
SDRAM module attributes
Registered/Buffered DQM,
address & control inputs and
On-card PLL
1Fh
22
SDRAM device attributes : General
+/- 10% voltage tolerance,
Burst Read Single bit Write
precharge all, auto precharge
0Eh
23
SDRAM cycle time @CAS latency of 2
7.5ns
10ns
10ns
12ns
75h
A0h
A0h
C0h
2
24
SDRAM access time @CAS latency of 2
5.4ns
6ns
6ns
7ns
54h
60h
60h
70h
2
25
SDRAM cycle time @CAS latency of 1
-
00h
26
SDRAM access time @CAS latency of 1
-
00h
27
Minimum row precharge time (=t
RP
)
15ns
20ns
20ns
20ns
0Fh
14h
14h
14h
28
Minimum row active to row active delay (t
RRD
)
15ns
15ns
20ns
20ns
0Fh
0Fh
14h
14h
29
Minimum RAS to CAS delay (=t
RCD
)
15ns
20ns
20ns
20ns
0Fh
14h
14h
14h
30
Minimum activate precharge time (=t
RAS
)
45ns
45ns
50ns
50ns
2Dh
2Dh
32h
32h
31
Module Row density
2 Row of 512MB
80h
32
Command and Address signal input setup time
1.5ns
1.5ns
2ns
2ns
15h
15h
20h
20h
33
Command and Address signal input hold time
0.8ns
0.8ns
1ns
1ns
08h
08h
10h
10h
34
Data signal input setup time
1.5ns
1.5ns
2ns
2ns
15h
15h
20h
20h
相關(guān)PDF資料 |
PDF描述 |
|---|---|
| M390S2858DTU-C7C | PC133/PC100 Low Profile Registered DIMM |
| M390S2858CT1 | SDRAM DIMM |
| M390S2858CT1-C7A | SDRAM DIMM |
| M390S2858CT1-C7C | SDRAM DIMM |
| M390S2858CTU-C7C | PC133/PC100 Low Profile Registered DIMM |
相關(guān)代理商/技術(shù)參數(shù) |
參數(shù)描述 |
|---|---|
| M390S2858CTU-C7C | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:PC133/PC100 Low Profile Registered DIMM |
| M390S2858DT1 | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:128Mx72 SDRAM DIMM with PLL & Register based on Stacked 128Mx4, 4Banks 8K Ref., 3.3V SDRAMs with SPD |
| M390S2858DT1-C7A | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:128Mx72 SDRAM DIMM with PLL & Register based on Stacked 128Mx4, 4Banks 8K Ref., 3.3V SDRAMs with SPD |
| M390S2858DT1-C7C | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:128Mx72 SDRAM DIMM with PLL & Register based on Stacked 128Mx4, 4Banks 8K Ref., 3.3V SDRAMs with SPD |
| M390S2858DTU | 制造商:SAMSUNG 制造商全稱:Samsung semiconductor 功能描述:PC133/PC100 Low Profile Registered DIMM |
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