參數(shù)資料
型號(hào)： M38K29F8LFP
元件分類： 微控制器/微處理器
英文描述： 8-BIT, FLASH, 8 MHz, MICROCONTROLLER, PQFP64
封裝： 14 X 14 MM, 0.80 MM PITCH, PLASTIC, LQFP-64
文件頁數(shù)： 81/151頁
文件大?。?/td> 1403K
代理商： M38K29F8LFP
38K2 Group
Rev.3.00
Oct 15, 2006
page 35 of 147
REJ03B0193-0300
Fig.38 Structure of USB interrupt source register
b7
b0
USB function/Endpoint 0
interrupt bit
USB function/Endpoint 1
interrupt bit
USB function/Endpoint 2
interrupt bit
USB function/Endpoint 3
interrupt bit
USB HUB/Endpoint 0 interrupt
bit
USB HUB/Endpoint 1 interrupt
bit
Suspend interrupt bit
Resume interrupt bit
EP00
EP01
EP02
EP03
EP10
EP11
SUS
RSM
0
USB interrupt source register (USBIREQ) [address 001716]
Bit name
Bit symbol
At reset
Function
H/W
S/W
O
O
This bit is set to “1” when any one of EP00 interrupt
source register’s bits at least is set to “1”.
This bit is cleared to “0” by clearing EP00 interrupt
source register to “0016”.
Writing to this bit causes no state change.
This bit is set to “1” when any one of EP01 interrupt
source register’s bits at least is set to “1”.
This bit is cleared to “0” by clearing EP01 interrupt
source register to “0016”.
Writing to this bit causes no state change.
This bit is set to “1” when any one of EP02 interrupt
source register’s bits at least is set to “1”.
This bit is cleared to “0” by clearing EP02 interrupt
source register to “0016”.
Writing to this bit causes no state change.
This bit is set to “1” when any one of EP03 interrupt
source register’s bits at least is set to “1”.
This bit is cleared to “0” by clearing EP03 interrupt
source register to “0016”.
Writing to this bit causes no state change.
This bit is set to “1” when any one of EP10 interrupt
source register’s bits at least is set to “1”.
This bit is cleared to “0” by clearing EP10 interrupt
source register to “0016”.
Writing to this bit causes no state change.
This bit is set to “1” when any one of EP11 interrupt
source register’s bits at least is set to “1”.
This bit is cleared to “0” by clearing EP11 interrupt
source register to “0016”.
Writing to this bit causes no state change.
0 : No interrupt request issued
1 : Interrupt request issued
This bit is set to “1” when detecting 3 ms or more of J-
state, using USB clock (fUSB) at 48 MHz.
“0” can be set by software, but “1” cannot be set.
This bit is set to “1” when the USB bus state changes
from J-state to K-state or SE0 in the resume interrupt
enable bit = “1”. It is also “1” in the condition of internal
clock stopped.
This bit is cleared to “0” by clearing the resume
interrupt enable bit.
Writing to this bit causes no state change.
W
R
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