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參數(shù)資料
| 型號(hào)： | M38C37ECMFS |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, UVPROM, 8 MHz, MICROCONTROLLER, CQCC80 |
| 封裝： | 0.80 MM PITCH, GLASS SEALED, CERAMIC, LCC-80 |
| 文件頁(yè)數(shù)： | 145/223頁(yè) |
| 文件大?。?/td> | 1698K |
| 代理商： | M38C37ECMFS |
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38C3 Group User’s Manual
HARDWARE
1-14
I/O PORTS
[Direction Registers (ports P2, P4, P50, P52–P57,
and P6–P8)]
The I/O ports P2, P4, P50, P52–P57, and P6–P8 have direction reg-
isters which determine the input/output direction of each individual
pin. Each bit in a direction register corresponds to one pin, each pin
can be set to be input port or output port.
When “0” is written to the bit corresponding to a pin, that pin be-
comes an input pin. When “1” is written to that bit, that pin becomes
an output pin.
If data is read from a pin set to output, the value of the port output
latch is read, not the value of the pin itself. Pins set to input are float-
ing. If a pin set to input is written to, only the port output latch is
written to and the pin remains floating.
[Direction Registers (ports P0 and P1)]
Ports P0 and P1 have direction registers which determine the input/
output direction of each individual port.
Each port in a direction register corresponds to one port, each port
can be set to be input or output.
When “0” is written to the bit 0 of a direction register, that port be-
comes an input port. When “1” is written to that port, that port be-
comes an output port. Bits 1 to 7 of ports P0 and P1 direction regis-
ters are not used.
Pull-up/Pull-down Control
By setting the PULL register A (address 001616) or the PULL register
B (address 001716), ports except for ports P3 and P51 can control
either pull-down or pull-up (pins that are shared with the segment
output pins for LCD are pull-down; all other pins are pull-up) with a
program.
However, the contents of PULL register A and PULL register B do
not affect ports programmed as the output ports.
Port P8 Output Selection
Ports P80 to P87 can be switched to N-channel open-drain output by
setting “1” to the port P8 output selection register.
Fig. 10 Structure of PULL register A and PULL register B
Pin
P00/SEG8 –
P07/SEG15
P10/SEG16 –
P17/SEG23
P20/SEG0 –
P27/SEG7
P30/SEG24 –
P37/SEG31
Name
Port P0
Port P1
Port P2
Port P3
Input/Output
Input/Output,
port unit
Input/Output,
port unit
Input/Output,
individual bits
Output,
individual bits
I/O format
CMOS compatible input
level
CMOS 3-state output
CMOS compatible input
level
CMOS 3-state output
CMOS compatible input
CMOS 3-state output
Non-port function
LCD segment output
Related SFRs
PULL register A
Segment output enable reg-
ister
PULL register A
Segment output enable reg-
ister
PULL register A
Segment output enable reg-
ister
Segment output enable reg-
ister
Ref. No.
(1)
(2)
Table 6 List of I/O port function (1)
Fig. 11 Structure of port P8 output selection register
FUNCTIONAL DESCRIPTION
P00–P07 pull-down
P10–P17 pull-down
P20–P27 pull-down
Not used
P70, P71 pull-up
P80–P87 pull-up
PULL register A
(PULLA : address 001616)
b7
b0
P40–P43 pull-up
P44–P47 pull-up
P50, P52, P53 pull-up
P54–P57 pull-up
P60–P63 pull-up
P64–P67 pull-up
Not used (return “0” when read)
0 : Disable
1 : Enable
PULL register B
(PULLB : address 001716)
b7
b0
Note: The contents of PULL register A and PULL register B
do not affect ports programmed as the output ports.
Not used (return “0” when read)
0 : CMOS output (in output mode)
1 : N-channel open-drain output
(in output mode)
Port P8 output selection register
(P8SEL : address 0018 16)
b7
b0
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