參數(shù)資料
型號： M38C12M4-XXXFP
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 4 MHz, MICROCONTROLLER, PQFP64
封裝： 14 X 14 MM, 0.80 MM PITCH, PLASTIC, LQFP-64
文件頁數(shù)： 11/59頁
文件大?。?/td> 704K
代理商： M38C12M4-XXXFP
Rev.2.40
Jun 14, 2004
page 19 of 56
38C1 Group
Fig. 15 Interrupt control
Fig. 16 Structure of interrupt-related registers
Interrupt request bit
Interrupt enable bit
Interrupt disable flag (I)
BRK instruction
Reset
Interrupt request
b7
b0
Interrupt edge selection register
INT0 interrupt edge selection bit
INT1 interrupt edge selection bit
Not used (return “0” when read)
(INTEDGE : address 003A16, initial value: 0016)
Interrupt request register 1
INT0 interrupt request bit
INT1 interrupt request bit
Not used (return “0” when read)
Timer X interrupt request bit
Timer Y interrupt request bit
Timer 1 interrupt request bit
Timer 3 interrupt request bit
Interrupt control register 1
INT0 interrupt enable bit
INT1 interrupt enable bit
Not used (Do not write “1” to these bits.)
Timer X interrupt enable bit
Timer Y interrupt enable bit
Timer 1 interrupt enable bit
Timer 3 interrupt enable bit
0 : No interrupt request issued
1 : Interrupt request issued
(IREQ1 : address 003C16, initial value: 0016)
(ICON1 : address 003E16, initial value: 0016)
Interrupt request register 2
CNTR0 interrupt request bit
CNTR1 interrupt request bit
Timer 2 interrupt request bit
Not used (returns “0” when read)
Serial I/O interrupt request bit
Key input interrupt request bit
AD conversion interrupt request bit
Not used (returns “0” when read)
(IREQ2 : address 003D16, initial value: 0016)
Interrupt control register 2
CNTR0 interrupt enable bit
CNTR1 interrupt enable bit
Timer 2 interrupt enable bit
Not used (Do not write “1” to this bit)
Serial I/O interrupt enable bit
Key input interrupt enable bit
AD conversion interrupt enable bit
Not used (Do not write “1” to this bit)
0 : Interrupts disabled
1 : Interrupts enabled
(ICON2 : address 003F16, initial value: 0016)
0 : Falling edge active
1 : Rising edge active
b7
b0
b7
b0
b7
b0
b7
b0
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