
38B5 Group User’s Manual
1-51
HARDWARE
FUNCTIONAL DESCRIPTION
P8
4
to P8
7
FLD output reverse function
P8
4
to P8
7
are provided with a function to reverse the polarity of the
FLD output. This function is useful in adjusting the polarity when
using an externally installed driver.
The output polarity can be reversed by setting “1” to bit 0 of the port
P8 FLD output control register.
P8
4
to P8
7
FLDRAM write disable function
This function can disable writing data in the RAM area correspond-
ing to P8
4
to P8
7
. This function can be set by setting “1” to bit 1 of the
port P8FLD output control register (address 0EFC
16
).
P8
4
to P8
7
Toff invalid function
P8
4
to P8
7
can output waveform in which Toff is invalid, when P8
4
to
P8
7
is selected FLD ports (See Figure 52).
The function is useful when using a 4 bits
→
16 bits decoder. The Toff
can be invalid by setting “1” to bit 2 of the port P8FLD output control
register (address 0EFC
16
).
P8
4
to P8
7
output delay function
P8
4
to P8
7
can output waveform in which is delayed for 16
μ
s, when
selecting FLD port and selecting Toff invalid function (See Figure
52). When using a 4 bits
→
16 bits decoder, the function can be use-
ful for prevention of leak radiation caused by phase discrepancy be-
tween segment output waveform and digit output waveform. This func-
tion can be set by setting “1” to bit 3 of the port P8FLD output control
register (address 0EFC
16
).
Dimmer signal output function
P6
3
can output the dimmer signal. When using a 4 bits
→
16 bits
decoder, the dimmer signal can be used as a control signal for a 4
bits
→
16 bits decoder. When using M35501FP, the dimmer signal
can be used as the CLK signal. The dimmer signal can be output by
setting “1” to bit 4 of the port P8FLD output control register (address
0EFC
16
).
Fig. 52 P8
4
to P8
7
FLD output waveform
Toff2 SET/RESET change function
The value of the Toff2 time set register is valid when gradation dis-
play mode is selected. The FLD ports output (set) the data of display
RAM at the end of the Toff1 time and output “0” (reset) at the end of
the Toff2 time, when bit 7 of the port P8FLD output control register is
“0”.
The FLD ports output (set) the data of display RAM at the end of the
Toff2 time and output “0” (reset) at the end of Tdisp time, when bit 7
of the port P8FLD output control register is “1”.
Fig. 53 Structure of port P8 FLD output control register
Port P8FLD output control register
(P8FLDCON: address 0EFC
16
)
P8
–P8
FLD output reverse bit
0: Output normally
1: Reverse output
P8
4
–P8
7
FLDRAM write disable bit
0: Operating normally
1: Write disabled
P8
4
–P8
7
Toff invalid bit
0: Operating normally
1: Toff invalid
P8
4
–P8
7
delay control bit
(Note)
0: No delay
1: Delay
P6
/AN
dimmer output control bit
0: Ordinary port
1: Dimmer output
Not used (“0” at reading)
Toff2 control bit
0: Gradation display data is reset at Toff2
(set at Toff1)
1: Gradation display data is set at Toff2
(reset at Tdisp)
b7
b0
Note:
Valid only when selecting FLD port and P8
4
–P8
7
Toff invalid function
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