參數(shù)資料
型號(hào): M38859M8-XXXHP
廠商: Renesas Technology Corp.
英文描述: SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
中文描述: 單芯片8位CMOS微機(jī)
文件頁數(shù): 46/103頁
文件大小: 1580K
代理商: M38859M8-XXXHP
45
3885 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
.
.
(2) START condition generating procedure using multi-master
1. Procedure example (The necessary conditions of the generat-
ing procedure are described as the following 2 to 5.
LDA
SEI
BBS 5, S1, BUSBUSY (BB flag confirming and branch pro
cess)
BUSFREE:
STA S0
(Writing of slave address value)
LDM #$F0, S1
(Trigger of START condition generating)
CLI
(Interrupt enabled)
(Taking out of slave address value)
(Interrupt disabled)
BUSBUSY:
CLI
(Interrupt enabled)
2. Use
Branch on Bit Set
of
BBS 5, $0014,
–”
for the BB flag
confirming and branch process.
3. Use
STA $12, STX $12
or
STY $12
of the zero page ad-
dressing instruction for writing the slave address value to the
I
2
C data shift register.
4. Execute the branch instruction of above 2 and the store instruc-
tion of above 3 continuously shown the above procedure
example.
5. Disable interrupts during the following three process steps:
BB flag confirming
Writing of slave address value
Trigger of START condition generating
When the condition of the BB flag is bus busy, enable interrupts
immediately.
(3) RESTART condition generating procedure
1. Procedure example (The necessary conditions of the generat-
ing procedure are described as the following 2 to 4.)
Execute the following procedure when the PIN bit is
0
.
LDM #$00, S1
LDA
SEI
STA S0
LDM #$F0, S1
CLI
(Select slave receive mode)
(Taking out of slave address value)
(Interrupt disabled)
(Writing of slave address value)
(
Trigger of RESTART condition generating
)
(Interrupt enabled)
2. Select the slave receive mode when the PIN bit is
0
. Do not
write
1
to the PIN bit. Neither
0
nor
1
is specified for the
writing to the BB bit.
The TRX bit becomes
0
and the S
DA
pin is released.
3. The S
CL
pin is released by writing the slave address value to
the I
2
C data shift register.
4. Disable interrupts during the following two process steps:
Writing of slave address value
Trigger of RESTART condition generating
(4) Writing to I
2
C status register
Do not execute an instruction to set the PIN bit to
1
from
0
and
an instruction to set the MST and TRX bits to
0
from
1
simulta-
neously. It is because it may enter the state that the S
CL
pin is
released and the S
DA
pin is released after about one machine
cycle. Do not execute an instruction to set the MST and TRX bits
to
0
from
1
simultaneously when the PIN bit is
1
. It is because
it may become the same as above.
(5) Process of after STOP condition generating
Do not write data in the I
2
C data shift register S0 and the I
2
C sta-
tus register S1 until the bus busy flag BB becomes
0
after
generating the STOP condition in the master mode. It is because
the STOP condition waveform might not be normally generated.
Reading to the above registers do not have the problem.
(6) ES0 bit switch
In standard clock mode when SSC =
00010
2
or in high-speed
clock mode, flag BB may switch to
1
if ES0 bit is set to
1
when
SDA is
L
.
Countermeasure:
Set ES0 to
1
when SDA is
H
.
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