參數(shù)資料
型號(hào)： M38858M7-XXXHP
廠商： Renesas Technology Corp.
英文描述： SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
中文描述： 單芯片8位CMOS微機(jī)
文件頁(yè)數(shù)： 59/103頁(yè)
文件大?。?/td> 1580K
代理商： M38858M7-XXXHP
3885 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
58
Fig. 52 Configuration of serialized IRQ control register
Register Explanation
The serialized IRQ function is configured and controlled by the se-
rialized IRQ request register (SERIRQ) and the serialized IRQ
control register (SERCON).
[Serialized IRQ control register (SERCON)] 001D
16
Bit 0 : Serialized IRQ enable bit (SIRQEN )
This bit enables/disables the serialized IRQ interface. When this
bit is
“
1
”
, use of serialized IRQ is enabled. Then P8
7
functions as
IRQ/Data line (SERIRQ) and P4
7
functions as CLKRUN.
Output structure of CLKRUN pin becomes N-channel open drain.
Bit 1 : LPC clock restart enable bit (RUNEN )
Setting this bit to
“
1
”
enables clock restart with
“
L
”
output of
CLKRUN.
Bit 2 : LPC clock stop inhibition bit (SUPEN )
Setting this bit to
“
1
”
makes CLKRUN output change to
“
L
”
for in-
hibiting the clock stop.
Bit 3 : Hardware IRQ1 request bit (SEIR1)
When this bit is
“
1
”
, OBF
0
status is directly connected to the IRQ
1
frame.
Bit 4 : Hardware IRQ12 request bit (SEIR12 )
When this bit is
“
1
”
, OBF
0
status is directly connected to IRQ12
frame.
Bit 5 : Hardware IRQx request bit (SEIRx )
When this bit is
“
1
”
, OBF
1
status is directly connected to the IRQ
x
frame.
Bit 6 : IRQ1/IRQ12 disable bit (SCH0EN )
This bit controls whether the serialized IRQ channel 0 transfers
the IRQ1 and IRQ12 frame to the host or not.
Bit 7 : IRQx output polarity bit (SCH1POL)
This bit selects IRx frame output level.
Serialized IRQ control register
Bit name
Function
Bit symbol
I
R
Q
W
R
Symbol
SERCON
Address
001D
16
When reset
00000000
2
S
E
N
Serialized IRQ enable bit
0 : Serialized IRQ disable
1 : Serialized IRQ enable
0 : Clock restart disable
1 : Clock restart enable
:
S
t
o
p
i
n
h
i
1
:
S
t
o
p
i
n
h
i
0
b
b
i
i
t
t
i
i
o
o
n
n
c
c
o
o
n
n
t
t
r
r
o
o
l
l
d
e
i
n
s
a
a
b
b
l
e
e
l
0 : No IRQ1 request
1 : OBF
0
synchronized IRQ1 request
L
P
C
c
l
o
c
k
r
e
s
t
a
r
t
e
n
a
b
l
e
b
i
t
LPC clock stop inhibition bit
Hardware IRQ1 request bit
RUNEN
S
U
P
E
N
S
E
I
R
1
b
7
b
6
b
5
b
4
b
3
b
2
b
1
b
0
H
a
r
d
w
a
r
e
I
R
Q
1
2
r
e
q
u
e
s
t
b
i
t
0 : No IRQ12 request
1 : OBF
0
synchronized IRQ12 request
:
N
o
I
R
Q
x
r
e
q
u
e
s
1
:
O
B
F
1
s
y
n
c
h
r
o
n
i
:
I
R
Q
1
/
I
R
Q
1
2
o
u
t
1
:
I
R
Q
1
/
I
R
Q
1
2
o
u
t
:
-
R
e
q
u
e
s
t
H
i
z
-
H
i
-
N
o
r
e
q
u
e
s
t
L
-
H
1
:
-
R
e
q
u
e
s
t
L
-
H
-
H
-
N
o
r
e
q
u
e
s
t
H
i
z
SEIRx
Hardware IRQx request bit
0
t
z
e
d
I
R
Q
x
r
e
q
u
e
s
t
S
E
I
R
1
2
SCH0EN
IR
Q
1
/
I
R
Q
1
2
d
i
s
a
b
l
e
b
i
t
0
p
p
u
u
t
t
e
d
n
i
s
a
a
b
b
l
e
l
e
IR
Q
x
o
u
t
p
u
t
p
o
l
a
r
i
t
y
b
i
t
0
z
-
i
z
-
H
-
H
H
i
i
z
z
i
z
-
H
i
z
S
C
H
1
P
O
L
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