參數(shù)資料
型號： M38854F2-HP
廠商： Renesas Technology Corp.
英文描述： SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
中文描述： 單芯片8位CMOS微機(jī)
文件頁數(shù)： 53/103頁
文件大小： 1580K
代理商： M38854F2-HP
3885 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
52
Basic Operation of LPC Interface
Set up steps for LPC interface is as below.
Set the LPC interface enable bit (bit3 of LPCCON) to
“
1
”
.
Choose which data bus buffer channel use.
Set the data bus buffer i enable bit (i = 0, 1) (bit 4 or 5 of
LPCCON) to
“
1
”
.
Set the slave address to LPCi address register L and H (i = 0, 1)
(LPC0ADL, LPC0ADH, LPC1ADL, LPC1ADH).
(1) Example of I/O write cycle
The I/O write cycle timing is shown in Figure 48. The standard
transfer cycle number of I/O write cycle is 13. The communication
starts from the falling edge of LFRAME.
The data on LAD [3:0] is monitored at every rising edge of LCLK.
1
st
clock: The last clock when LFRAME is
“
Low
”
. The host send
“
0000
2
”
on LAD [3:0] for communication start.
2
nd
clock: LFRAME is
“
High
”
. The host send
“
001X
2
”
on LAD
[3:0] to inform the cycle type as I/O write.
From 3
rd
clock to 6
th
clock : In these four cycles , the host sends
16-bit slave address. The 3885 compares it with the LPCi ad-
dress register H and L (i = 0, 1).
3
rd
clock: The slave address bit [15:12].
4
th
clock: The slave address bit [11:8].
5
th
clock: The slave address bit [7:4].
6
th
clock: The slave address bit [3:0].
7
th
clock and 8
th
clock are used for one data byte transfer. The
data is written to the input data bus buffer (DBBINi, i = 0, 1)
7
th
clock: The host sends the data bit [3:0].
8
th
clock: The host sends the data bit [7:4].
9
th
clock and 10
th
clock are for turning the communication direc-
tion from the host
→
the peripheral to the slave
→
the host.
9
th
clock: The host outputs
“
1111
2
”
on LAD [3:0].
10
th
clock: The LAD [3:0] is set to tri-state by the host to
turn the communication direction.
11
th
clock: The 3885 outputs
“
0000
2
”
(SYNC OK) to LAD [3:0] for
acknowledgment.
12
th
clock: The 3885 outputs
“
1111
2
”
to LAD [3:0]. In this timing
the address bit 2 is latched to XA2i (bit3 of DBBSTSi),
IBFi (bit 1 of DBBSTSi) is set to
“
1
”
and IBF interrupt
signal is generated.
13
th
clock: The LAD [3:0] is set to tri-state by the host to turn the
communication direction.
(2) Example for I/O read cycle
The I/O read cycle timing is shown in Figure 49. The standard
transfer cycle number of I/O read cycle is 13. The data on LAD
[3:0] is monitored at every rising edge of LCLK. The communica-
tion starts from the falling edge of LFRAME.
1
st
clock: The last clock when LFRAME is
“
Low
”
. The host sends
“
0000
2
”
on LAD [3:0] for communication start.
2
nd
clock: LFRAME is
“
High
”
. The host sends
“
000X
2
”
on LAD
[3:0] to inform the cycle type as I/O read.
From 3
rd
clock to 6th clock: In these four cycles , the host sends
16-bit slave address. The 3885 compares it with the LPCi ad-
dress register H or L (i = 0, 1).
3
rd
clock: The slave address bit [15:12].
4
th
clock: The slave address bit [11:8].
5
th
clock: The slave address bit [7:4].
6
th
clock: The slave address bit [3:0].
7
th
clock and 8
th
clock are used for turning the communication di-
rection from the host
→
the peripheral to the peripheral
→
the host.
7
th
clock: The host outputs
“
1111
2
”
on LAD [3:0].
8
th
clock: The LAD [3:0] is set to tri-state by the host to
turn the communication direction.
9
th
clock: The 3885 outputs
“
0000
2
”
(SYNC OK) to LAD [3:0] for
acknowledgment.
10
th
clock and 11
th
clock are used for one data byte transfer from
the output data bus buffer i (DBBOUTi) or data bus buffer status
register i (DBBSTSi).
10
th
clock: The 3885 sends the data bit [3:0].
11
th
clock: The 3885 sends the data bit [7:4].
12
th
clock: The 3885 outputs
“
1111
2
”
to LAD [3:0]. In this timing
OBFi (bit 2 of DBBSTSi) is cleared to
“
0
”
and OBE
interrupt signal is generated.
13
th
clock: The LAD [3:0] is set to tri-state by the host to turn the
communication direction.
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