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參數(shù)資料
| 型號： | M38827G5-XXXHP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 4 MHz, MICROCONTROLLER, PQFP80 |
| 封裝： | 12 X 12 MM, 0.50 MM PITCH, PLASTIC, LQFP-80 |
| 文件頁數(shù)： | 24/64頁 |
| 文件大?。?/td> | 619K |
| 代理商： | M38827G5-XXXHP |
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Rev.1.01
Nov 14, 2005
page 28 of 60
REJ03B0089-0101
3882 Group
LPC INTERFACE
LPC interface function is base on Low Pin Count (LPC) Interface
Specification, Revision 1.0. The 3882 supports only I/O read cycle
and
I/O write cycle. There are two channels of bus buffers to the host.
The functions of Input Data Bus Buffer, Output Data Bus Buffer
and Data Bus Buffer Status Register are the same as that of the
8042, 3880 group, 3881 group,3886 group and 3885 group. It can
be written in or read out from the host controller through LPC in-
terface. LPC interface function block diagram is shown in Figure
23.
Functional input or output pins of LPC interface are shared with
Port 8 (P80–P86). Setting the LPC interface enable bit (bit3 of
LPCCON) to “1” enables LPC interface. Enabling channel i (i = 0,
1) of the data bus buffer is controlled by the data bus buffer i (i =
0, 1) enable bits (bit 4 or bit 5 of LPCCON).
The slave addresses of the data bus buffer channel i (i = 0, 1) are
definable by setting LPCi (i = 0, 1) address register H/L
(LPC0ADL, LPC0ADH, LPC1ADL, LPC1ADH). The bit 2 value of
LPCi address register L is not decoded. This bit returns “0” when
the internal CPU read. The bit 2 of slave address is latched to
XA2i flag when the host controller writes the data.
The input buffer full (IBF) interrupt occurs when the host controller
writes the data. The output buffer empty (OBE) interrupt is gener-
ated when the host controller reads out the data. The 3882
merges two input buffer full (IBF) interrupt requests and two output
buffer empty (OBE) interrupt requests as shown in Figure 24.
Table 9 Function explanation of the control pin in LPC interface
P80/LAD0
I/O
These pins communicate address, control and data
information between the host and the data bus buffer of
the 3882.
P81/LAD1
I/O
P82/LAD2
I/O
P83/LAD3
I/O
P84/LFRAME
I
Input the signal to indicate the start of new cycle and
termination of abnormal communication cycles.
I
Input the LPC synchronous clock signal.
P85/LRESET
I
Input the signal to reset the LPC interface function.
Pin name
Input/
Output
Function
P86/LCLK
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相關(guān)代理商/技術(shù)參數(shù) |
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| M38827G6-XXXHP | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
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| M38827G9-XXXHP | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
| M38827GA-XXXHP | 制造商:RENESAS 制造商全稱:Renesas Technology Corp 功能描述:SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
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