參數(shù)資料
型號： M38514E6-XXXFP
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 4 MHz, MICROCONTROLLER, PDSO42
封裝： 0.450 INCH, 0.80 MM PITCH, PLASTIC, SSOP-42
文件頁數(shù)： 31/91頁
文件大?。?/td> 1161K
代理商： M38514E6-XXXFP
Rev.1.01
Oct 15, 2003
page 37 of 89
3851 Group (Built-in 24 KB or more ROM)
START/STOP
condition
control register
Oscillation
frequency
f(XIN) (MHz)
Fig. 39 Address data communication format
Fig. 38 Structure of I2C START/STOP condition control register
Note: Do not set an odd number to the START/STOP condition set bit (SSC4 to SSC0).
Table 14 Recommended set value to START/STOP condition set bits (SSC4–SSC0) for each oscillation frequency
Main clock
divide ratio
System
clock
φ
(MHz)
SCL release time
(
s)
Setup time
(
s)
Hold time
(
s)
8
4
2
8
2
XXX11010
XXX11000
XXX00100
XXX01100
XXX01010
XXX00100
3.375
s (13.5 cycles)
3.125
s (12.5 cycles)
2.5
s (2.5 cycles)
3.25
s (6.5 cycles)
2.75
s (5.5 cycles)
2.5
s (2.5 cycles)
6.75
s (27 cycles)
6.25
s (25 cycles)
5.0
s (5 cycles)
6.5
s (13 cycles)
5.5
s (11 cycles)
5.0
s (5 cycles)
3.375
s (13.5 cycles)
3.125
s (12.5 cycles)
2.5
s (2.5 cycles)
3.25
s (6.5 cycles)
2.75
s (5.5 cycles)
2.5
s (2.5 cycles)
4
1
2
1
b7b0
I2C START/STOP condition
control register
START/STOP condition set bit
SCL/SDA interrupt pin polarity
selection bit
0 :Falling edge active
1 :Rising edge active
SCL/SDA interrupt pin selection bit
0 :SDA valid
1 :SCL valid
Reserved
Do not write “1” to this bit.
SIS SIP SSC4SSC3SSC2SSC1SSC0
(S2D : address 003016)
S
Slave addressR/W
A
Data
A/A
P
A
Data
7 bits
“0”
1 to 8 bits
(1) A master-transmitter transnmits data to a slave-receiver
S
Slave addressR/W
A
Data
A
P
A
Data
7 bits
“1”
1 to 8 bits1 to 8 bits
(2) A master-receiver receives data from a slave-transmitter
7 bits
“0”
8 bits
(3) A master-transmitter transmits data to a slave-receiver with a 10-bit address
1 to 8 bits1 to 8 bits
S
R/W
A
Slave address
1st 7 bits
Slave address
2nd bytes
A
AData
Data
P
A/A
7 bits
“0”
8 bits
(4) A master-receiver receives data from a slave-transmitter with a 10-bit address
S : START condition
A : ACK bit
Sr : Restart condition
P : STOP condition
R/W : Read/Write bit
7 bits
“1”
1 to 8 bits1 to 8 bits
S
R/W
A
Slave address
1st 7 bits
Slave address
2nd bytes
A
Sr
Slave address
1st 7 bits
R/W
A
Data
P
A
: Master to slave
: Slave to master
A
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