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REVISION HISTORY
Rev.
Date
Description
Page
Summary
3850 Group (Spec.H/A) Data Sheet
(2/3)
57
58
59
60
62
63
65
77
78
79
86
Explanations of “qErase All Blocks Command (2016/2016)” are partly revised.
Explanations of “qBlock Erase Command (2016/D016)” are partly revised.
Explanations of “Status Register (SRD)” are partly revised.
Figure 62 is partly revised.
Explanations of “qROM Code Protect Function (in Parallel I/O Mode)” is partly
revised.
Figure 63 is partly revised.
Contents of “(2) Parallel I/O Mode” are revised.
(Explanations, figures, and tables of Pages 61–67 in Rev. 2.0 except “Parallel
I/O Mode” and “User ROM and Boot ROM Areas” are eliminated.)
Explanations of “(3) Standard serial I/O Mode” are partly revised.
Figure 65 is partly revised.
Limits of VI (CNVss) into Table 18 are revised.
Item of VIL, VIH into Table 19 are eliminated.
Figures and tables of Pages 79–84 in Rev. 2.0 are eliminated.
Explanations of “A-D converter” are partly eliminated.
Clause name and explanations of “Differences among 3850 group (standard),
3850 group (spec. H), and 3850 group (spec. A)” are partly revised.
“Electric Characteristic Differences Among Mask ROM, Flash Memory, and One
Time PROM Version MCUs” is added.
Test conditions of Low-speed mode of Icc are partly added.
3.00 May. 29, 2002
3.01 Jun. 20, 2003
SCLK
→ SCLK1
Power dissipation is partly revised.
In high-speed mode .... 34mW
→ In high-speed mode
Except M38507F8FP/SP ... 32.5mW
M38507F8/SP .... 37.5mW
Mitsubishi
→ Renesas Technology
Delete the following : Products under development or planning: the development
schedule and specification may be revised without notice. The development of
planning products may be stopped.
Fig.55 System clock generating circuit block diagram (Single-chip mode)
Note is partly added.
Fig.56 State transition of system clock
Note is partly added.
the “Mitsubishi MCU Technical information ” Homepage
(http://www.infomicom.maec.co.jp/indexe.html)
→the “Renesas Technology” Homepage Rom ordering
(http://www.renesas.com/eng/rom)
Table 28 Electrical characteristics (2)
Separate spec.H and spec.A
VT+–VT- RXD, SCLK
→ RXD, SCLK1, SCLK2, SIN2
Table 29 Electrical characteristics (2)
Limit of “L” input current (at Pull-up) is added
Table 31 Electrical characteristics (3)
Limit of power source current is partly revised.
Limit of M38507F8FP/SP is added
Limit of the high-speed mode [f(XIN)=8MHZ] is added.
Limit of the high-speed mode [f(XIN)=8MHZ(in WIT state)] is added.
Limit of the middle-speed mode [f(XIN)=12.5MHZ] is added.
Limit of the middle-speed mode [f(XIN)=12.5MHZ(in WIT state)] is added.
2
8
49
50
79
85
85,86
86
88