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參數(shù)資料
| 型號(hào)： | M38503M4A-XXXSP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 6.25 MHz, MICROCONTROLLER, PDIP42 |
| 封裝： | 13 X 36.72 MM, 1.78 MM PITCH, PLASTIC, SDIP-42 |
| 文件頁(yè)數(shù)： | 37/90頁(yè) |
| 文件大?。?/td> | 899K |
| 代理商： | M38503M4A-XXXSP |
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Rev.2.10
2005.11.14
page 40 of 86
REJ03B0093-0210
3850 Group (Spec.A)
Fig. 46 State transitions of system clock
CM4 : Port Xc switch bit
0 : I/O port function (stop oscillating)
1 : XCIN-XCOUT oscillating function
CM5 : Main clock (XIN- XOUT) stop bit
0 : Operating
1 : Stopped
CM7, CM6: Main clock division ratio selection bit
b7 b6
0
0 :
φ = f(XIN)/2 ( High-speed mode)
0
1 :
φ = f(XIN)/8 (Middle-speed mode)
1
0 :
φ = f(XCIN)/2 (Low-speed mode)
1
1 : Not available
Notes
Reset
CM
4
“1
”
←→
“0
”
CM
4
“0
” ←→
“1
”
CM
6
“1
” ←→
“0
”
CM
4
“1
” ←→
“0
”
CM
6
“1
” ←→
“0
”
CM
7
“1
”
←→
“0
”
CM
4
“1
”
←→
“0
”
CM
5
“1
”
←→
“0
”
CM6
“1”
←→ “0”
CM6
“1”
←→ “0”
CPU mode register
b7
b4
CM
7
“0” ←→
“1”
CM
6
“1” ←→
“0”
(CPUM : address 003B16)
CM7 = 0
CM6 = 1
CM5 = 0 (8 MHz oscillating)
CM4 = 0 (32 kHz stopped)
Middle-speed mode
(f(
φ) = 1 MHz)
CM7 = 0
CM6 = 1
CM5 = 0 (8 MHz oscillating)
CM4 = 1 (32 kHz oscillating)
Middle-speed mode
(f(
φ) = 1 MHz)
CM7 = 0
CM6 = 0
CM5 = 0 (8 MHz oscillating)
CM4 = 0 (32 kHz stopped)
High-speed mode
(f(
φ) = 4 MHz)
CM7 = 1
CM6 = 0
CM5 = 0 (8 MHz oscillating)
CM4 = 1 (32 kHz oscillating)
Low-speed mode
(f(
φ)=16 kHz)
CM7 = 1
CM6 = 0
CM5 = 1 (8 MHz stopped)
CM4 = 1 (32 kHz oscillating)
Low-speed mode
(f(
φ)=16 kHz)
CM7 = 0
CM6 = 0
CM5 = 0 (8 MHz oscillating)
CM4 = 1 (32 kHz oscillating)
High-speed mode
(f(
φ) = 4 MHz)
1 : Switch the mode by the allows shown between the mode blocks. (Do not switch between the modes directly without an allow.)
2 : The all modes can be switched to the stop mode or the wait mode and return to the source mode when the stop mode or the wait mode is
ended.
3 : Timer operates in the wait mode.
4 : After STP instruction is released, the count source which had set by bit 2 (timer 12 count source selection bit) of the timer count source set
register at executing the STP instruction is supplied to timer 1. Accordingly, when bit 0 of MISRG is “0” and the timer 12 count source
selection bit is “0” (f(XIN)/16 or f(XCIN)/16), a delay of approximately 1 ms occurs automatically in the high/middle-speed mode. A delay of
approximately 256 ms occurs automatically in the low-speed mode (at f(XIN) = 8 MHz, f(XCIN) = 32 kHz). When the timer 12 count source
selection bit is “1” (f(XCIN)), a delay of approximately 16 ms occurs regardless of the operation mode.
5 : Wait until oscillation stabilizes after oscillating the main clock XIN before the switching from the low-speed mode to middle/high-speed
mode.
6 : When the mode is switched to the middle-speed mode by the middle-speed mode automatic switch set bit of MISRG, the waiting time set
by the middle-speed mode automatic switch wait time set bit is automatically generated, and then the mode is switched to the middle-
speed mode.
7 : The example assumes that 8 MHz is being applied to the XIN pin and 32 kHz to the XCIN pin.
φ indicates the internal clock.
Middle-speed mode
automatic switch set bit
"1"
Middle-speed mode
automatic switch start bit
"1"
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