參數(shù)資料
型號： M38503M4A-XXXSP
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 6.25 MHz, MICROCONTROLLER, PDIP42
封裝： 13 X 36.72 MM, 1.78 MM PITCH, PLASTIC, SDIP-42
文件頁數(shù)： 14/59頁
文件大小： 885K
代理商： M38503M4A-XXXSP
Rev.2.13
Apr 17, 2009
Page 21 of 56
REJ03B0125-0213
3850 Group (Spec.A QzROM version)
Fig 15. Interrupt control
Fig 16. Structure of interrupt-related registers
Interrupt disable flag (I)
Interrupt request
Interrupt request bit
Interrupt enable bit
BRK instruction
Reset
Interrupt edge selection register
(INTEDGE : address 003A16)
INT0 interrupt edge selection bit
INT1 interrupt edge selection bit
INT2 interrupt edge selection bit
INT3 interrupt edge selection bit
Serial I/O2 / INT3 interrupt source bit
0 : INT3 interrupt selected
1 : Serial I/O2 interrupt selected
Not used (returns “0” when read)
0 : Falling edge active
1 : Rising edge active
Interrupt request register 1
(IREQ1 : address 003C16)
INT0 interrupt request bit
Reserved
INT1 interrupt request bit
INT2 interrupt request bit
INT3 / Serial I/O2 interrupt request bit
Reserved
Timer X interrupt request bit
Timer Y interrupt request bit
0 : No interrupt request issued
1 : Interrupt request issued
Interrupt request register 2
(IREQ2 : address 003D16)
Timer 1 interrupt request bit
Timer 2 interrupt request bit
Serial I/O1 reception interrupt request bit
Serial I/O1 transmit interrupt request bit
CNTR0 interrupt request bit
CNTR1 interrupt request bit
AD converter interrupt request bit
Not used (returns “0” when read)
0 : No interrupt request issued
1 : Interrupt request issued
Interrupt control register 1
(ICON1 : address 003E16)
INT0 interrupt enable bit
Reserved (Do not write “1” to this bit.)
INT1 interrupt enable bit
INT2 interrupt enable bit
INT3 / Serial I/O2 interrupt enable bit
Reserved (Do not write “1” to this bit.)
Timer X interrupt enable bit
Timer Y interrupt enable bit
0 : Interrupts disabled
1 : Interrupts enabled
Interrupt control register 2
(ICON2 : address 003F16)
0 : Interrupts disabled
1 : Interrupts enabled
Timer 1 interrupt enable bit
Timer 2 interrupt enable bit
Serial I/O1 reception interrupt enable bit
Serial I/O1 transmit interrupt enable bit
CNTR0 interrupt enable bit
CNTR1 interrupt enable bit
AD converter interrupt enable bit
Not used (returns “0” when read)
(Do not write “1” to this bit.)
b7
b0
b7
b0
b7
b0
b7
b0
b7
b0
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