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參數(shù)資料
| 型號： | M38503G4A-XXXFP |
| 元件分類： | 微控制器/微處理器 |
| 英文描述： | 8-BIT, MROM, 6.25 MHz, MICROCONTROLLER, PDSO42 |
| 封裝： | 8.40 X 17.5 MM, 0.80 MM PITCH, PLASTIC, SSOP-42 |
| 文件頁數(shù)： | 15/59頁 |
| 文件大?。?/td> | 885K |
| 代理商： | M38503G4A-XXXFP |
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Rev.2.13
Apr 17, 2009
Page 22 of 56
REJ03B0125-0213
3850 Group (Spec.A QzROM version)
TIMERS
The 3850 group (spec.A) has four timers: timer X, timer Y, timer
1, and timer 2.
The division ratio of each timer or prescaler is given by 1/(n + 1),
where n is the value in the corresponding timer or prescaler latch.
All timers are count down. When the timer reaches “0016”, an
underflow occurs at the next count pulse and the corresponding
timer latch is reloaded into the timer and the count is continued.
When a timer underflows, the interrupt request bit corresponding
to that timer is set to “1”.
Fig 17. Structure of timer XY mode register
Fig 18. Structure of timer count source selection register
Timer 1 and Timer 2
The count source of prescaler 12 is the oscillation frequency
which is selected by timer 12 count source selection bit. The
output of prescaler 12 is counted by timer 1 and timer 2, and a
timer underflow sets the interrupt request bit.
Timer X and Timer Y
Timer X and Timer Y can each select in one of four operating
modes by setting the timer XY mode register.
(1) Timer Mode
The timer counts the count source selected by Timer count
source selection bit.
(2) Pulse Output Mode
The timer counts the count source selected by Timer count
source selection bit. Whenever the contents of the timer reach
“0016”, the signal output from the CNTR0 (or CNTR1) pin is
inverted. If the CNTR0 (or CNTR1) active edge selection bit is
“0”, output begins at “H”.
If it is “1”, output starts at “L”. When using a timer in this mode,
set the corresponding port P27 (or port P40) direction register to
output mode.
(3) Event Counter Mode
Operation in event counter mode is the same as in timer mode,
except that the timer counts signals input through the CNTR0 or
CNTR1 pin.
When the CNTR0 (or CNTR1) active edge selection bit is “0”,
the rising edge of the CNTR0 (or CNTR1) pin is counted.
When the CNTR0 (or CNTR1) active edge selection bit is “1”,
the falling edge of the CNTR0 (or CNTR1) pin is counted.
(4) Pulse Width Measurement Mode
If the CNTR0 (or CNTR1) active edge selection bit is “0”, the
timer counts the selected signals by the count source selection bit
while the CNTR0 (or CNTR1) pin is at “H”. If the CNTR0 (or
CNTR1) active edge selection bit is “1”, the timer counts it while
the CNTR0 (or CNTR1) pin is at “L”.
The count can be stopped by setting “1” to the timer X (or timer
Y) count stop bit in any mode. The corresponding interrupt
request bit is set each time a timer underflows.
<Notes>
When switching the count source by the timer 12, X and Y count
source bits, the value of timer count is altered in unconsiderable
amount owing to generating of a thin pulses in the count input
signals.
Therefore, select the timer count source before set the value to
the prescaler and the timer.
When timer X/timer Y underflow while executing the instruction
which sets “1” to the timer X/timer Y count stop bits, the timer
X/ timer Y interrupt request bits are set to “1”. Timer X/Timer Y
interrupts are received if these interrupts are enabled at this time.
The timing which interrupt is accepted has a case after the
instruction which sets “1” to the count stop bit, and a case after
the next instruction according to the timing of the timer
underflow. When this interrupt is unnecessary, set “0” (disabled)
to the interrupt enable bit and then set “1” to the count stop bit.
b7
Timer XY mode register
(TM : address 002316)
Timer X operating mode bit
b1 b0
0 0: Timer mode
0 1: Pulse output mode
1 0: Event counter mode
1 1: Pulse width measurement mode
CNTR0 active edge selection bit
0: Interrupt at falling edge
Count at rising edge in event
counter mode
1: Interrupt at rising edge
Count at falling edge in event
counter mode
Timer X count stop bit
0: Count start
1: Count stop
Timer Y operating mode bits
b5 b4
0 0: Timer mode
0 1: Pulse output mode
1 0: Event counter mode
1 1: Pulse width measurement mode
CNTR1 active edge selection bit
0: Interrupt at falling edge
Count at rising edge in event
counter mode
1: Interrupt at rising edge
Count at falling edge in event
counter mode
Timer Y count stop bit
0: Count start
1: Count stop
b0
Timer count source selection register
(TCSS : address 002816)
Timer X count source selection bit
0 : f(XIN)/16 (f(XCIN)/16 at low-speed mode)
1 : f(XIN)/2 (f(XCIN)/2 at low-speed mode)
Timer Y count source selection bit
0 : f(XIN)/16 (f(XCIN)/16 at low-speed mode)
1 : f(XIN)/2 (f(XCIN)/2 at low-speed mode)
Timer 12 count source selection bit
0 : f(XIN)/16 (f(XCIN)/16 at low-speed mode)
1 : f(XCIN)
Not used (returns “0” when read)
b7
b0
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