參數(shù)資料
型號： M38503E4-XXXSP
元件分類： 微控制器/微處理器
英文描述： 8-BIT, OTPROM, 4 MHz, MICROCONTROLLER, PDIP42
封裝： 0.600 INCH, 1.78 MM PITCH, PLASTIC, SDIP-42
文件頁數(shù)： 9/55頁
文件大?。?/td> 867K
代理商： M38503E4-XXXSP
14
3850 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
Fig. 10 Interrupt control
Fig. 11 Structure of interrupt-related registers (1)
b7
b0
b7
b0
b7
b0
b7
b0
b7
b0
Interrupt edge selection register
INT0 active edge selection bit
INT1 active edge selection bit
INT2 active edge selection bit
INT3 active edge selection bit
Reserved(Do not write “1” to this bit)
Not used (returns “0” when read)
(INTEDGE : address 003A16)
Interrupt request register 1
INT0 interrupt request bit
Reserved
INT1 interrupt request bit
INT2 interrupt request bit
INT3 interrupt request bit
Reserved
Timer X interrupt request bit
Timer Y interrupt request bit
Interrupt control register 1
INT0 interrupt enable bit
Reserved(Do not write "1" to this bit)
INT1 interrupt enable bit
INT2 interrupt enable bit
INT3 interrupt enable bit
Reserved(Do not write "1" to this bit)
Timer X interrupt enable bit
Timer Y interrupt enable bit
0 : No interrupt request issued
1 : Interrupt request issued
(IREQ1 : address 003C16)
(ICON1 : address 003E16)
Interrupt request register 2
Timer 1 interrupt request bit
Timer 2 interrupt request bit
Serial I/O reception interrupt request bit
Serial I/O transmit interrupt request bit
CNTR0 interrupt request bit
CNTR1 interrupt request bit
AD converter interrupt request bit
Not used (returns “0” when read)
(IREQ2 : address 003D16)
Interrupt control register 2
Timer 1 interrupt enable bit
Timer 2 interrupt enable bit
Serial I/O reception interrupt enable bit
Serial I/O transmit interrupt enable bit
CNTR0 interrupt enable bit
CNTR1 interrupt enable bit
AD converter interrupt enable bit
Not used (returns “0” when read)
(Do not write “1” to this bit)
0 : Interrupts disabled
1 : Interrupts enabled
(ICON2 : address 003F16)
0 : Falling edge active
1 : Rising edge active
0 : No interrupt request issued
1 : Interrupt request issued
0 : Interrupts disabled
1 : Interrupts enabled
Interrupt disable flag (I)
Interrupt request
Interrupt request bit
Interrupt enable bit
BRK instruction
Reset
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