
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
3826 Group
25
TIMERS
The 3826 group has five timers: timer X, timer Y, timer 1, timer 2,
and timer 3. Timer X and timer Y are 16-bit timers, and timer 1,
timer 2, and timer 3 are 8-bit timers.
All timers are down count timers. When the timer reaches “0016”,
an underflow occurs at the next count pulse and the correspond-
ing timer latch is reloaded into the timer and the count is contin-
ued. When a timer underflows, the interrupt request bit corre-
sponding to that timer is set to “1”.
Read and write operation on 16-bit timer must be performed for
both high- and low-order bytes. When reading a 16-bit timer, read
the high-order byte first. When writing to a 16-bit timer, write the
low-order byte first. The 16-bit timer cannot perform the correct
operation when reading during the write operation, or when writing
during the read operation.
Fig. 20 Timer block diagram
“1”
P55/CNTR1
“0”
"10"
"00","01","11"
P54/CNTR0
Q
T
S
“0”
“1”
“0”
Q D
“0”
Q D
“1”
“0”
“1”
"10"
Q
T
S
“0”
“1”
“0”
“1”
P43/
φ/TOUT
XCIN
“0”
“1”
CNTR0 active
edge switch bit
Timer 1 count source
selection bit
Real time port
control bit “0”
f(XIN)/16
(f(XCIN)/16
when
φ = XCIN/2)
CNTR1 active
edge switch bit
Timer Y stop
control bit
Falling edge detection
Period
measurement mode
Timer Y
interrupt
request
Pulse width HL continuously
measurement mode
Rising edge detection
Timer Y
operating
mode bits
Timer X
interrupt
request
Timer X mode register
write signal
P43 direction register
Pulse output mode
P54 latch
Timer X stop
control bit
Timer X write
control bit
Latch
ing mode bits
“00”,“01”,“11”
Pulse width
measurement
mode
CNTR0 active
edge switch bit
Pulse output mode
P54 direction register
TOUT output
active edge
switch bit “0”
Timer 2 write
control bit
TOUT output
control bit
Timer 3 count
source selection bit
Timer 2
interrupt
request
Timer 3
interrupt
request
Timer 2 count source
selection bit
Timer 1
interrupt
request
Data bus
Real time port
control bit “1”
Real time port
control bit “1”
Timer Y (low) (8)
Timer Y (high) (8)
Timer 3 latch (8)
Timer 3 (8)
Timer 1 latch (8)
Timer 1 (8)
Timer 2 latch (8)
Timer 2 (8)
Timer X (low) (8)
Timer X (high) (8)
Timer X (low) latch (8)
Timer X (high) latch (8)
Timer Y (low) latch (8)
Timer Y (high) latch (8)
Latch
TOUT output
control bit
P43 latch
f(XIN)/16
(f(XCIN)/16 when
φ = XCIN/2)
f(XIN)/16
(f(XCIN)/16 when
φ = XCIN/2)
f(XIN)/16
(f(XCIN)/16 when
φ = XCIN/2)
f(XIN)/16
(f(XCIN)/16 when
φ = XCIN/2)
P52 direction register
P52 data for
real time port
P53 data for
real time port
P52 latch
P53 direction register
P53 latch
φ
φ output control bit
P52/RTP0
P53/RTP1