參數(shù)資料
型號: M3823AGF-XXXFP
廠商: Renesas Technology Corp.
英文描述: SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
中文描述: 單芯片8位CMOS微機
文件頁數(shù): 19/76頁
文件大?。?/td> 896K
代理商: M3823AGF-XXXFP
Rev.2.02 Jun 19, 2007 page 19 of 73
REJ03B0146-0202
3823 Group
Fig. 14 Port block diagram (2)
(
7
)
P
o
r
t
P
4
5
(
8
)
P
o
r
t
P
4
6
Serial I/O clock-
synchronized selection bit
Serial I/O enable bit
Serial I/O mode selection bit
Serial I/O enable bit
Direction register
Port latch
S
e
r
i
a
l
I
/
O
c
l
o
c
k
o
u
t
p
u
S
t
D
a
t
a
b
u
s
e
r
i
a
l
I
/
O
c
l
o
c
k
i
n
p
u
t
P
u
l
l
-
u
p
c
o
n
t
r
o
l
(10) Ports P5
2,
P5
3
Direction register
Port latch
Data bus
Pull-up control
R
e
a
D
l
a
t
t
i
m
a
e
f
o
p
r
o
r
r
t
a
c
l
o
t
i
n
m
t
r
e
o
l
b
o
i
r
t
t
e
p
Direction register
Port latch
D
a
t
a
b
u
s
Pull-up control
(1
2
)
P
o
r
t
s
P
5
5
,
P
5
7
CNTR
1
interrupt input
A/D trigger interrupt input
(1
1
)
P
o
r
t
P
5
4
D
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
r
P
o
r
t
l
a
t
c
h
D
a
t
a
b
u
s
Pull-up control
T
i
m
e
r
X
o
p
e
r
a
t
i
n
g
m
i
o
d
e
b
i
t
T
m
e
r
o
u
t
p
u
t
CNTR
0
interrupt input
(Pulse output mode selection)
D
a
t
a
b
u
s
Serial I/O enable bit
Transmit enable bit
D
i
r
e
c
t
i
S
s
e
o
r
r
i
a
a
l
y
I
n
/
O
c
o
r
o
u
n
t
o
p
u
u
s
t
)
(
s
y
n
c
h
r
o
n
o
u
s
h
P-Channel output disabled selection bit
S
R
D
S
O
U
P
-
c
h
a
n
n
e
P
o
r
t
l
a
t
c
h
o
n
r
e
g
i
s
t
e
r
P
u
l
l
-
u
p
c
o
n
t
r
o
l
P
4
5
/
T
x
D
,
P
4
7
/
Y
/
T
l
o
u
t
p
u
t
d
i
s
a
b
l
e
b
i
t
As
s
e
y
i
a
n
l
c
I
h
/
O
r
o
o
n
u
o
t
u
p
s
u
t
s
e
p
r
n
i
a
s
l
e
I
/
l
O
e
o
t
i
u
o
t
n
p
u
b
t
i
Sy
n
c
h
r
o
n
o
u
s
r
i
c
t
D
a
t
a
b
u
s
S
e
r
i
a
l
I
/
O
r
e
a
d
y
o
u
t
p
u
t
Port latch
Serial I/O mode selection bit
Serial I/O enable bit
S
RDY
,S
OUT
output enable bit
D
i
r
e
c
t
i
o
n
r
e
g
i
s
t
e
r
Pull-up control
P-Channel output disabled selection bit
S
R
D
S
O
U
P
-
c
h
a
n
n
e
Synchronous serial I/O output pin selection bit
Synchronous serial I/O output
P
4
5
/
T
x
D
,
P
4
7
/
Y
/
T
l
o
u
t
p
u
t
d
i
s
a
b
l
e
b
i
t
(9) Port P4
7
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