參數(shù)資料
型號(hào)： M38239GC-XXXFP
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 10 MHz, MICROCONTROLLER, PQFP80
封裝： 14 X 20 MM, 0.80 MM PITCH, PLASTIC, QFP-80
文件頁(yè)數(shù)： 46/64頁(yè)
文件大?。?/td> 922K
代理商： M38239GC-XXXFP
Rev.2.02
Jun 19, 2007
page 48 of 73
REJ03B0146-0202
3823 Group
WATCHDOG TIMER
The watchdog timer gives a mean of returning to the reset status
when a program cannot run on a normal loop (for example, be-
cause of a software run-away). The watchdog timer consists of an
8-bit counter.
Initial Value of Watchdog Timer
At reset or writing to the watchdog timer control register, each
watchdog timer is set to “FF16.” Instructions such as STA, LDM
and CLB to generate the write signals can be used.
The written data in bits 0 to 5 are not valid, and the above values
are set.
Bits 7 and 6 can be rewritten only once after reset.
After rewriting it is disable to write any data to this bit. These bits
become “0” after reset.
Standard Operation of Watchdog Timer
The watchdog timer is in the stop state at reset and the watchdog
timer starts to count down by writing an optional value in the
watchdog timer control register. An internal reset occurs at an un-
derflow of the watchdog timer. Then, reset is released after the
reset release time is elapsed, the program starts from the reset
vector address. Normally, writing to the watchdog timer control
register before an underflow of the watchdog timer is pro-
grammed. If writing to the watchdog timer control register is not
executed, the watchdog timer does not operate.
When reading the watchdog timer control register is executed, the
contents of the high-order 6-bit counter and the STP instruction bit
(bit 6), and the count source selection bit (bit 7) are read out.
Bit 6 of Watchdog Timer Control Register
When bit 6 of the watchdog timer control register is “0”, the MCU
enters the stop mode by execution of STP instruction.
Just after releasing the stop mode, the watchdog timer restarts
counting (Note). When executing the WIT instruction, the watch-
dog timer does not stop.
When bit 6 is “1”, execution of STP instruction causes an internal
reset. When this bit is set to “1” once, it cannot be rewritten to
“0” by program. Bit 6 is “0” at reset.
The time until the underflow of the watchdog timer register after
writing to the watchdog timer control register is executed is as fol-
lows (when the bit 7 of the watchdog timer control register is “0”) ;
at frequency/2/4/8 mode (f(XIN)) = 8 MHz): 32.768 ms
at low-speed mode (f(XCIN) = 32 KHz): 8.19s
■ Note
The watchdog timer continues to count even during the wait time set
by timer 1 and timer 2 to release the stop state and in the wait
mode. Accordingly, do not underflow the watchdog timer in this time.
Fig. 47 Block diagram of Watchdog timer
Fig. 48 Structure of Watchdog timer control register
Fig. 49 Timing of reset output
Internal reset
signal
Watchdog timer
detection
=32msec (f(XIN)=8MHZ)
f(XIN)
Watchdog timer H (for read-out of high-order 6 bit)
“FF16” is set to watchdog timer by writing to these bits.
Watchdog timer count source selection bit
0: f(XIN)/1024 (f(SUB)/1024 at low-speed mode)
1: f(XIN)/4 (f(SUB)/1024 at low-speed mode)
STP instruction function selection bit
0: Entering stop mode by execution of STP instruction
1: Internal reset by execution of STP instruction
Watchdog timer control register (Address 003716)
WDTCON
b7
b0
Note : Bits 6 and 7 can be rewritten only once after reset.
After rewriting it is disable to write any data to this bit.
XIN
Data bus
XCIN
Internal system clock
selection bit (bit 7 of
the CPU mode register)
1/1024
Watchdog timer
H (6)
Watchdog timer count
source selection bit
Reset
circuit
Undefined instruction
Reset
“FF16” is set when
watchdog timer control
register is written to.
Internal reset
RESET
Wait until reset release
Watchdog timer
L (2)
STP instruction
STP instruction bit
1/4
“0”
“1”
“0”
On-chip oscillator mode
control bit
On-chip oscillator
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