參數(shù)資料
型號： M38239G7-XXXFP
廠商： Renesas Technology Corp.
英文描述： SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
中文描述： 單芯片8位CMOS微機
文件頁數(shù)： 53/76頁
文件大小： 896K
代理商： M38239G7-XXXFP
Rev.2.02 Jun 19, 2007 page 53 of 73
REJ03B0146-0202
3823 Group
Fig. 56 Clock generating circuit block diagram
Oscillation Control
(1) Stop Mode
If the STP instruction is executed, the internal clock
φ
stops at an
“H” level, and X
IN
and X
CIN
oscillators stop. Timer 1 is set to
“FF
16
” and timer 2 is set to “01
16
”.
Either X
IN
or X
CIN
divided by 16 is input to timer 1 as count
source, and the output of timer 1 is connected to timer 2. The bits
of the timer 123 mode register except bit 4 are cleared to “0”. Set
the timer 1 and timer 2 interrupt enable bits to disabled (“0”) be-
fore executing the STP instruction. Oscillator restarts at reset or
when an external interrupt is received, but the internal clock
φ
is
not supplied to the CPU until timer 2 underflows. This allows timer
for the clock circuit oscillation to stabilize.
Execution of the STP instruction sets the LCD enable bit (bit 3 of
the LCD mode register) to “0” and the LCD panel turns off.To
make the LCD panel turn on after returning from the stop mode,
set the LCD enable bit to “1”.
(2) Wait Mode
If the WIT instruction is executed, only the system clock
φ
stops at
an "H" state. The states of main clock, on-chip oscillator and sub
clock are the same as the state before executing the WIT instruc-
tion, and oscillation does not stop. Since supply of system clock
φ
is started immediately after the interrupt is received, the instruc-
tion can be executed immediately.
Timing
φ
(Internal system clock)
Main clock stop bit
Timer 2
Timer 1
1/2
1/4
XIN
XOUT
WIT
instruction
STP instruction
S
R
Q
STP instruction
S
R
Q
S
R
Q
Interrupt request
Interrupt disable flag 1
Reset
1/2
“1”
“0”
Timer 1
count source
selection bit
“0”
“1”
Timer 2
count source
selection bit
Low-speed mode
Frequency/2/4/8
mode
(Note 1)
Frequency/8 mode
Frequency/2/4
mode or low-
speed mode
Internal system clock selection bit
Main clock division
ratio selection bit
“1”
“1”
“0”
“0”
Notes 1:
When using the low-speed mode, set the port X
C
switch bit to “1” .
2:
Although a feed-back resistor exists on-chip, an external feed-back resistor may be needed depending
on conditions.
Frequency/4
mode
control bit
1/2
XCOUT
XCIN
Port XC
switch bit
“0”
“1”
On-chip
oscillator
On-chip oscillator
control bit
f(SUB)
(Note 2)
相關PDF資料
PDF描述
M38239G7-XXXHP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
M38239G8-XXXFP 72-Mbit DDR-II SRAM 2-Word Burst Architecture; Architecture: DDR-II CIO, 2 Word Burst; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 1.7 to 1.9 V
M38239G8-XXXHP 72-Mbit DDR-II SIO SRAM 2-Word Burst Architecture; Architecture: DDR-II SIO, 2 Word Burst; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 1.7 to 1.9 V
M38239G9-XXXFP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
M38239G9-XXXHP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
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