參數(shù)資料
型號: M38239G3-XXXFP
廠商: Renesas Technology Corp.
英文描述: 72-Mbit DDR-II SRAM 2-Word Burst Architecture; Architecture: DDR-II CIO, 2 Word Burst; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 1.7 to 1.9 V
中文描述: 單芯片8位CMOS微機
文件頁數(shù): 49/76頁
文件大?。?/td> 896K
代理商: M38239G3-XXXFP
Rev.2.02 Jun 19, 2007 page 49 of 73
REJ03B0146-0202
3823 Group
PERIPHERAL FUNCTION EXTENSION REGISTER
The serial I/O transfer direction can be switched by setting the bit
0 in the peripheral function expansion register to “1”. This function
is valid only when the bit 6 in the serial I/O control register is set to
“1” (when the clock synchronous serial I/O is selected). P4
7
can
be selected as the output pin of the clock synchronous serial I/O
by setting the bit 1 in the peripheral function expansion register to
“1”. When setting P4
7
to the S
OUT
pin, set the bit 7 in the port P4
direction register to “1”. This function is valid only when the bit 6 in
the serial I/O control register to “1” (when the clock synchronous
serial I/O is selected). P-channel output of T
X
D and S
OUT
can be
disabled by the bits 2 and 3 in the peripheral function expansion
register. Set the bit 4 in the UART control register to “1” after se-
lecting the pin to disable the P-channel output. X
CIN
frequency
signal can be output from the port P4
1
by setting the bit 4 in the
peripheral function expansion register to “1”. Set the bit 0 in the
φ
output control register and the bit 1 in the port P4 direction regis-
ter to “1” to output the X
CIN
frequency signal.
Fig. 50 Structure of peripheral function extension register
Transfer direction selection bit (valid when UART is used)
0 : LSB first
1 : MSB first
Synchronous serial I/O output pin selection bit
0:P4
5
/T
X
D pin
1:P4
7
/S
RDY
/S
OUT
pin
P-channel output disabled selection bit
00: P4
5
/T
X
D pin
01: The bit 4 in the UART control register is invalid
10: P4
5
/T
X
D pin or P47/S
RDY
/S
OUT
pin
11: P4
7
/S
RDY
/S
OUT
pin
Output clock selection bit
0:
φ
clock output
1: X
CIN
frequency signal output
Not used (returns “0” when read)
(Do not write “1” to this bit)
Peripheral function extension register (Address: 0030
16
)
EXP
b
7
b
0
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M38239G4-XXXHP 72-Mbit DDR-II SRAM 2-Word Burst Architecture; Architecture: DDR-II CIO, 2 Word Burst; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 1.7 to 1.9 V
M38239G5-XXXFP 72-Mbit DDR-II SRAM 2-Word Burst Architecture; Architecture: DDR-II CIO, 2 Word Burst; Density: 72 Mb; Organization: 2Mb x 36; Vcc (V): 1.7 to 1.9 V
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