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參數(shù)資料
| 型號： | M38239G2-XXXFP |
| 廠商： | Renesas Technology Corp. |
| 英文描述： | SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
| 中文描述： | 單芯片8位CMOS微機(jī) |
| 文件頁數(shù)： | 16/76頁 |
| 文件大?。?/td> | 896K |
| 代理商： | M38239G2-XXXFP |
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Rev.2.02 Jun 19, 2007 page 16 of 73
REJ03B0146-0202
3823 Group
I/O PORTS
Direction Registers (ports P2, P4
1
-P4
7
, and
P5-P7)
The 3823 group has 49 programmable I/O pins arranged in seven
I/O ports (ports P0–P2, P4
1
–P4
7
and P5-P7). The I/O ports P2,
P4
1
–P4
7
and P5-P7 have direction registers which determine the
input/output direction of each individual pin. Each bit in a direction
register corresponds to one pin, and each pin can be set to be in-
put port or output port.
When “0” is written to the bit corresponding to a pin, that pin be-
comes an input pin. When “1” is written to that bit, that pin be-
comes an output pin.
If data is read from a pin set to output, the value of the port output
latch is read, not the value of the pin itself. Pins set to input are
floating. If a pin set to input is written to, only the port output latch
is written to and the pin remains floating.
Direction Registers (ports P0 and P1)
Ports P0 and P1 have direction registers which determine the in-
put/output direction of each individual port.
Each port in a direction register corresponds to one port, each port
can be set to be input or output. When “0” is written to the bit 0 of
a direction register, that port becomes an input port. When “1” is
written to that port, that port becomes an output port. Bits 1 to 7 of
ports P0 and P1 direction registers are not used.
Ports P3 and P4
0
These ports are only for input.
Pull-up/Pull-down Control
By setting the PULL register A (address 0016
16
) or the PULL reg-
ister B (address 0017
16
), ports except for port P4
0
can control
either pull-down or pull-up (pins that are shared with the segment
output pins for LCD are pull-down; all other pins are pull-up) with
a program.
However, the contents of PULL register A and PULL register B do
not affect ports programmed as the output ports.
Fig. 12 Structure of PULL register A and PULL register B
P0
0
–P0
7
pull-down
P1
0
–P1
7
pull-down
P2
0
–P2
7
pull-up
P3
4
–P3
7
pull-down
P7
0
, P7
1
pull-up
Not used (return “0” when read)
PULL register A
(PULLA: address 0016
16
)
b7
b
0
P4
1
–P4
3
pull-up
P4
4
–P4
7
pull-up
P5
0
–P5
3
pull-up
P5
4
–P5
7
pull-up
P6
0
–P6
3
pull-up
P6
4
–P6
7
pull-up
Not used (return “0” when read)
:
1
:
0
D
E
i
n
s
a
a
b
b
l
e
e
l
PULL register B
(PULLB : address 0017
16
)
b7
b0
Note
: The contents of PULL register A and PULL register B
do not affect ports programmed as the output port.
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| M38239G2-XXXHP | SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
| M38239G3-XXXFP | 72-Mbit DDR-II SRAM 2-Word Burst Architecture; Architecture: DDR-II CIO, 2 Word Burst; Density: 72 Mb; Organization: 4Mb x 18; Vcc (V): 1.7 to 1.9 V |
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