參數(shù)資料
型號: M38234G7-XXXFP
廠商: Renesas Technology Corp.
英文描述: SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
中文描述: 單芯片8位CMOS微機
文件頁數(shù): 31/76頁
文件大?。?/td> 896K
代理商: M38234G7-XXXFP
Rev.2.02 Jun 19, 2007 page 31 of 73
REJ03B0146-0202
3823 Group
Timer Y
Timer Y is a 16-bit timer that can be selected in one of four modes.
(1) Timer Mode
The timer counts f(X
IN
)/16 (or f(SUB)/16 in low-speed mode).
(2) Period Measurement Mode
CNTR
1
interrupt request is generated at rising/falling edge of
CNTR
1
pin input signal. Simultaneously, the value in timer Y latch
is reloaded in timer Y and timer Y continues counting down. Ex-
cept for the above-mentioned, the operation in period
measurement mode is the same as in timer mode.
The timer value just before the reloading at rising/falling of CNTR
1
pin input signal is retained until the timer Y is read once after the
reload.
The rising/falling timing of CNTR
1
pin input signal is found by
CNTR
1
interrupt. When using a timer in this mode, set the corre-
sponding port P5
5
direction register to input mode.
(3) Event Counter Mode
The timer counts signals input through the CNTR
1
pin.
Except for this, the operation in event counter mode is the same
as in timer mode. When using a timer in this mode, set the corre-
sponding port P5
5
direction register to input mode.
(4) Pulse Width HL Continuously Measurement
Mode
CNTR
1
interrupt request is generated at both rising and falling
edges of CNTR
1
pin input signal. Except for this, the operation in
pulse width HL continuously measurement mode is the same as in
period measurement mode. When using a timer in this mode, set
the corresponding port P5
5
direction register to input mode.
Note on CNTR
1
interrupt active edge selection
CNTR
1
interrupt active edge depends on the CNTR
1
active edge
switch bit. However, in pulse width HL continuously measurement
mode, CNTR
1
interrupt request is generated at both rising and
falling edges of CNTR
1
pin input signal regardless of the setting of
CNTR
1
active edge switch bit.
Fig. 24 Structure of timer Y mode register
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