參數(shù)資料
型號(hào)： M38223M4MXXXGP
元件分類： 微控制器/微處理器
英文描述： 8-BIT, MROM, 8 MHz, MICROCONTROLLER, PQFP80
封裝： 14 X 14 MM, 0.65 MM PITCH, PLASTIC, QFP-80
文件頁(yè)數(shù)： 33/46頁(yè)
文件大?。?/td> 910K
代理商： M38223M4MXXXGP
69
ATmega165A/PA/325A/PA/3250A/PA/645A/P/6450A/P [DATASHEET]
8285E–AVR–02/2013
MOSI/PCINT10 – Port B, Bit 2
MOSI: SPI Master Data output, Slave Data input for SPI. When the SPI is enabled as a Slave, this pin is configured
as an input regardless of the setting of DDB2. When the SPI is enabled as a Master, the data direction of this pin is
controlled by DDB2. When the pin is forced to be an input, the pull-up can still be controlled by the PORTB2 bit.
PCINT10, Pin Change Interrupt Source 10: The PB2 pin can serve as an external interrupt source.
SCK/PCINT9 – Port B, Bit 1
SCK: Master Clock output, Slave Clock input pin for SPI. When the SPI is enabled as a Slave, this pin is configured
as an input regardless of the setting of DDB1. When the SPI is enabled as a Master, the data direction of this pin is
controlled by DDB1. When the pin is forced to be an input, the pull-up can still be controlled by the PORTB1 bit.
PCINT9, Pin Change Interrupt Source 9: The PB1 pin can serve as an external interrupt source.
SS/PCINT8 – Port B, Bit 0
SS: Slave Port Select input. When the SPI is enabled as a Slave, this pin is configured as an input regardless of
the setting of DDB0. As a Slave, the SPI is activated when this pin is driven low. When the SPI is enabled as a
Master, the data direction of this pin is controlled by DDB0. When the pin is forced to be an input, the pull-up can
still be controlled by the PORTB0 bit
PCINT8, Pin Change Interrupt Source 8: The PB0 pin can serve as an external interrupt source.
Table 14-4 and Table 14-5 relate the alternate functions of Port B to the overriding signals shown in Figure 14-5 on
page 66. SPI MSTR INPUT and SPI SLAVE OUTPUT constitute the MISO signal, while MOSI is divided into SPI
MSTR OUTPUT and SPI SLAVE INPUT.
Table 14-4.
Overriding signals for alternate functions in PB7:PB4.
Signal name
PB7/OC2A/PCINT15
PB6/OC1B/PCINT14
PB5/OC1A/PCINT13
PB4/OC0A/PCINT12
PUOE
0
PUOV
0
DDOE
0
DDOV
0
PVOE
OC2A ENABLE
OC1B ENABLE
OC1A ENABLE
OC0A ENABLE
PVOV
OC2A
OC1B
OC1A
OC0A
PTOE
–
DIEOE
PCINT15 PCIE1
PCINT14 PCIE1
PCINT13 PCIE1
PCINT12 PCIE1
DIEOV
1
DI
PCINT15 INPUT
PCINT14 INPUT
PCINT13 INPUT
PCINT12 INPUT
AIO
–
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