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    參數(shù)資料
    型號(hào): M38203E4HP
    元件分類: 微控制器/微處理器
    英文描述: 8-BIT, OTPROM, 4 MHz, MICROCONTROLLER, PQFP80
    封裝: 0.50 MM PITCH, PLASTIC, QFP-80
    文件頁數(shù): 6/67頁
    文件大?。?/td> 1099K
    代理商: M38203E4HP
    13
    MITSUBISHI MICROCOMPUTERS
    3820 Group
    SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
    I/O PORTS
    Direction Registers (ports P2, P41–P47, and
    P5–P7)
    The 3820 group has 43 programmable I/O pins arranged in seven
    I/O ports (ports P0–P2 and P4–P7). The I/O ports P2, P41–P47,
    and P5–P7 have direction registers which determine the input/out-
    put direction of each individual pin. Each bit in a direction register
    corresponds to one pin, each pin can be set to be input port or
    output port.
    When “0” is written to the bit corresponding to a pin, that pin be-
    comes an input pin. When “1” is written to that bit, that pin be-
    comes an output pin.
    If data is read from a pin set to output, the value of the port output
    latch is read, not the value of the pin itself. Pins set to input are
    floating. If a pin set to input is written to, only the port output latch
    is written to and the pin remains floating.
    Direction Registers (ports P0 and P1)
    Ports P0 and P1 have direction registers which determine the in-
    put /output direction of each individual port.
    Each port in a direction register corresponds to one port, each
    port can be set to be input or output.
    When “0” is written to the bit 0 of a direction register, that port be-
    comes an input port. When “1” is written to that port, that port be-
    comes an output port.
    Bits 1 to 7 of ports P0 and P1 direction registers are not used.
    Ports P3 and P40
    These ports are only for input.
    Pull-up/Pull-down Control
    By setting the PULL register A (address 001616) or the PULL reg-
    ister B (address 001716), ports except for port P40 can control ei-
    ther pull-down or pull-up (pins that are shared with the segment
    output pins for LCD are pull-down; all other pins are pull-up) with a
    program.
    However, the contents of PULL register A and PULL register B do
    not affect ports programmed as the output ports.
    Fig. 4 Structure of PULL register A and PULL register B
    PULL register A
    (PULLA : address 0016 16)
    0 : Disable
    1 : Enable
    70
    Note : The contents of PULL register A
    and PULL register B do not affect
    ports programmed as the output ports.
    PULL register B
    (PULLB : address 0017 16)
    70
    P00–P07 pull-down
    P10–P17 pull-down
    P20–P27 pull-up
    P30–P37 pull-down
    P70, P71 pull-up
    Not used (return "0" when read)
    P41–P43 pull-up
    P44–P47 pull-up
    P50–P53 pull-up
    P54–P57 pull-up
    P60, P61 pull-up
    Not used (return "0" when read)
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