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參數(shù)資料
| 型號(hào)： | M381L3223ETM-LC5 |
| 廠商： | SAMSUNG SEMICONDUCTOR CO. LTD. |
| 英文描述： | 184pin Unbuffered Module based on 256Mb E-die 64/72-bit ECC/Non ECC |
| 中文描述： | 184pin緩沖模塊，基于256Mb電子模具64/72-bit ECC的/非ECC |
| 文件頁數(shù)： | 4/19頁 |
| 文件大?。?/td> | 287K |
| 代理商： | M381L3223ETM-LC5 |
DDR SDRAM
Revision 1.0 December, 2003
256MB, 512MB DDR466 Unbuffered DIMM
AC Timing Parameters and Specifications
Parameter
Symbol
- C5(DDR466@CL=3)
Unit
Note
Min
Max
Row cycle time
tRC
60
ns
Refresh row cycle time
tRFC
70
ns
Row active time
tRAS
40
70K
ns
RAS to CAS delay
tRCD
18
ns
Row precharge time
tRP
18
ns
Row active to Row active delay
tRRD
10
ns
Write recovery time
tWR
15
ns
Internal write to read command delay
tWTR
2
tCK
Clock cycle time
CL=3.0
tCK
4.3
10
ns
16
CL=2.5
6
12
ns
Clock high level width
tCH
0.45
0.55
tCK
Clock low level width
tCL
0.45
0.55
tCK
DQS-out access time from CK/CK
tDQSCK
-0.55
+0.55
ns
Output data access time from CK/CK
tAC
-0.65
+0.65
ns
Data strobe edge to ouput data edge
tDQSQ
-
0.4
ns
13
Read Preamble
tRPRE
0.9
1.1
tCK
Read Postamble
tRPST
0.4
0.6
tCK
CK to valid DQS-in
tDQSS
0.72
1.28
tCK
Write preamble setup time
tWPRES
0
ps
5
Write preamble
tWPRE
0.25
tCK
Write postamble
tWPST
0.4
0.6
tCK
4
DQS falling edge to CK rising-setup time
tDSS
0.2
tCK
DQS falling edge from CK rising-hold time
tDSH
0.2
tCK
DQS-in high level width
tDQSH
0.35
tCK
DQS-in low level width
tDQSL
0.35
tCK
Address and Control Input setup time
tIS
0.6
ns
h,7~10
Address and Control Input hold time
tIH
0.6
ns
h,7~10
Data-out high impedence time from CK/CK
tHZ
-
tAC max
ns
3
Data-out low impedence time from CK/CK
tLZ
tAC min
tAC max
ns
3
Mode register set cycle time
tMRD
2
tCK
DQ & DM setup time to DQS, slew rate 0.5V/ns
tDS
0.4
ns
i, j
DQ & DM hold time to DQS, slew rate 0.5V/ns
tDH
0.4
ns
i, j
DQ & DM input pulse width
tDIPW
1.75
ns
9
Control & Address input pulse width for each input
tIPW
2.2
ns
9
Refresh interval time
Up to 128Mb
tREFI
7.8
us
6
256Mb, 512Mb, 1Gb
us
Output DQS valid window
tQH
tHP
-tQHS
-ns
12
Clock half period
tHP
min
tCH/tCL
-
ns
11, 12
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