參數(shù)資料
      型號: M38198MC-083FP
      廠商: Mitsubishi Electric Corporation
      英文描述: SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
      中文描述: 單芯片8位CMOS微機(jī)
      文件頁數(shù): 50/60頁
      文件大?。?/td> 664K
      代理商: M38198MC-083FP
      50
      3819 Group
      SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
      MITSUBISHI MICROCOMPUTERS
      NOTES ON PROGRAMMING
      Processor Status Register
      The contents of the processor status register (PS) after a reset are
      undefined, except for the interrupt disable flag (I) which is “1”. Af-
      ter a reset, initialize flags which affect program execution. In
      particular, it is essential to initialize the index X mode (T) and the
      decimal mode (D) flags because of their effect on calculations.
      Interrupts
      The contents of the interrupt request bits do not change immedi-
      ately after they have been written. After writing to an interrupt
      request register, execute at least one instruction before performing
      a BBC or BBS instruction.
      Decimal Calculations
      To calculate in decimal notation, set the decimal mode flag (D)
      to “1”, then execute an ADC or SBC instruction. Only the ADC
      and SBC instructions yield proper decimal results. After execut-
      ing an ADC or SBC instruction, execute at least one instruction
      before executing a SEC, CLC, or CLD instruction.
      In decimal mode, the values of the negative (N), overflow (V),
      and zero (Z) flag are invalid.
      The carry flag can be used to indicate whether a carry or borrow
      has occurred. Initialize the carry flag before each calculation.
      Clear the carry flag before an ADC and set the flag before an
      SBC.
      Timers
      If a value n (between 0 and 255) is written to a timer latch, the fre-
      quency division ratio is 1/(n+1).
      Multiplication and Division Instructions
      The index X mode (T) and the decimal mode (D) flags do not af-
      fect the MUL and DIV instruction.
      The execution of these instructions does not change the con-
      tents of the processor status register.
      Ports
      The contents of the port direction registers cannot be read. The
      following cannot be used:
      the data transfer instruction (LDA, etc.)
      the operation instruction when the index X mode flag (T) is “1”
      the addressing mode which uses the value of a direction register
      as an index
      the bit-test instruction (BBC or BBS, etc.) to a direction register
      the read-modify-write instructions (ROR, CLB, or SEB, etc.) to a
      direction register.
      Use instructions such as LDM and STA, etc., to set the port direc-
      tion registers.
      Serial I/O
      When using an external clock, input “H” to the external clock input
      pin and clear the serial I/O interrupt request bit before executing
      serial I/O transfer and serial I/O automatic transfer.
      When using the internal clock, set the synchronous clock to inter-
      nal clock, then clear the serial I/O interrupt request bit before
      executing a serial I/O transfer and serial I/O automatic transfer.
      A-D Converter
      The comparator uses internal capacitors whose charge will be lost
      if the clock frequency is too low.
      Make sure that f(X
      IN
      ) is 500 kHz or more during an A-D conver-
      sion.
      Do not execute the STP or WIT instruction during an A-D conver-
      sion.
      Instruction Execution Time
      The instruction execution time is obtained by multiplying the fre-
      quency of the internal clock
      φ
      by the number of cycles needed to
      execute an instruction.
      The number of cycles required to execute an instruction is shown
      in the list of machine instructions. The frequency of the internal
      clock
      φ
      is half of the X
      IN
      or X
      CIN
      frequency.
      At the STP Instruction Release
      At the STP instruction release, all bits of the timer 12 mode regis-
      ter are cleared.
      The X
      COUT
      drivability selection bit (the CPU mode register) is set
      to “1” (high drive) in order to start oscillating.
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