參數(shù)資料
    

    


    


    
型號(hào)：
M38197M2-XXXFP

    

    
廠商：
Mitsubishi Electric Corporation

    

    
英文描述：
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER

    

    
中文描述：
單芯片8位CMOS微機(jī)

    

    
文件頁(yè)數(shù)：
29/60頁(yè)

    

    
文件大?。?/td>
664K

    

    
代理商：
M38197M2-XXXFP


    

    

    

	
    
    
    

    
    
	
    29
    3819 Group
    SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
    MITSUBISHI MICROCOMPUTERS
    Table GA-2.  P6
    7
    /S
    RDY1
    /CS selection
    (2.4) When Selecting the External Clock
    When selecting the external clock, the internal clock and the set-
    ting of transfer interval with the serial I/O automatic transfer
    interval register are invalid, but the serial I/O output pin S
    OUT1
     and
    the internal transfer clock can be controlled from the outside by
    setting the S
    RDY1
     pin to the CS (input) pin.
    When the CS input is “L”, the S
    OUT1
     pin and the internal transfer
    clock are enabled.
    When the CS input is “H”, the S
    OUT1
     pin goes to high impedance
    state and the internal transfer clock goes to “H”.
    Select the function of the P6
    7
    /S
    RDY1
    /CS/S
    CLK12
     with the following
    registers (refer to Table GA-2):
    G
    the bit 4 (SC1
    4
    ) and the bit 6 (SC1
    6
    ) of the serial I/O1 control
    register
    G
    the bit 0 (SIOAC
    0
    ) of the serial I/O automatic transfer control
    register
    Switch the CS pin from “L” to “H” or from “H” to “L” during “H” of the
    transfer clock (S
    CLK11
     input) after transferring 1-byte data.
    When selecting the external clock, set the external clock to “L” af-
    ter 9 cycles or more of the internal clock 
    φ
     after setting the start
    bit. After transferring 1-byte data, leave 11 cycles or more of the
    internal clock 
    φ
     free for the transfer interval.
    When not using the CS input, note that the S
    OUT
     pin will not go to
    high impedance state, even after transfer is completed.
    When not using the CS input, or when CS is “L”, control the exter-
    nal clock because the data in the serial I/O register will continue to
    shift while the external clock is input, even after the completion of
    automatic transfer (Note that the automatic transfer interrupt re-
    quest bit is set and the bit 1 of the serial I/O automatic transfer
    register is cleared at the point when the specified number of bytes
    of data have been transferred.)
    SC1
    6
    0
    SC1
    4
    0
    1
    SIOAC
    0
    0
    1
    P6
    7
    /S
    RDY1
    /CS
    P6
    7
    S
    RDY1
    CS
    Note :
     SC1
    4
    : S
    RDY1
     output selection bit
    SC1
    6
    : Synchronous clock selection bit
    SIOAC
    0
    : Automatic transfer control bit
    Fig. GA-10  Timing during serial I/O automatic transfer (external clock selected)
    X
    Bit 1 write signal of serial I/O
    automatic transfer control
    register
    Serial I/O output
    S
    OUT
    Serial I/O input
    S
    IN
    Note:
     Data marked with X is invalid.
    Bit 1 of serial I/O automatic 
    transfer control register
    Write signal from RAM to 
    serial I/O1 register
    Write signal from serial I/O1 
    register to  RAM 
    Transfer clock
    (internal) 
    Data pointer
    CS
    n-1
    n
    DO
    0
    X
    Transfer clock
    S
    CLK 
    input
    External input
    X
    DO
    1
     DO
    2
     DO
    3
     DO
    4
     DO
    5
     DO
    6
     DO
    7
    DI
    0
    DI
    1
    DI
    2
    DI
    3
    DI
    4
    DI
    5
    DI
    6
    DI
    7
    X
    X
    X
    
    
    
    
    
    


    


    

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