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    參數(shù)資料
    型號: M38190EA-XXXFP
    廠商: Mitsubishi Electric Corporation
    英文描述: SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
    中文描述: 單芯片8位CMOS微機
    文件頁數(shù): 33/60頁
    文件大?。?/td> 664K
    代理商: M38190EA-XXXFP
    33
    3819 Group
    SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
    MITSUBISHI MICROCOMPUTERS
    FLDC Mode Registers (FLDM 1, FLDM 2)
    0036
    16
    , 0037
    16
    The FLDC mode register 1 (address 0036
    16
    ) and FLDC mode reg-
    ister 2 (address 0037
    16
    ) are a seven bit register and an eight bit
    register respectively which are used to control the FLD automatic
    display and set the blanking time T
    scan
    for key-scan.
    Fig. KA-2 Structure of FLDC mode register 1
    Fig. KA-3 Structure of FLDC mode register 2
    T
    scan
    control bits
    b1
    b0
    0 0 : 0 FLD digit interrupt (at rising edge of each digit)
    0 1 : 1
    T
    disp
    1 0 : 2
    T
    disp
    1 1 : 3
    T
    disp
    T
    off
    control bits
    (Setting of digit/segment OFF time)
    b5
    b4
    b3
    b2
    0 0 0 0 : 1/16
    T
    disp
    0 0 0 1 : 2/16
    T
    disp
    0 0 1 0 : 3/16
    T
    disp
    0 0 1 1 : 4/16
    T
    disp
    0 1 0 0 : 5/16
    T
    disp
    0 1 0 1 : 6/16
    T
    disp
    0 1 1 0 : 7/16
    T
    disp
    0 1 1 1 : 8/16
    T
    disp
    1 0 0 0 : 9/16
    T
    disp
    1 0 0 1 : 10/16
    T
    disp
    1 0 1 0 : 11/16
    T
    disp
    1 0 1 1 : 12/16
    T
    disp
    1 1 0 0 : 13/16
    T
    disp
    1 1 0 1 : 14/16
    T
    disp
    1 1 1 0 : 15/16
    T
    disp
    1 1 1 1 : 16/16
    T
    disp
    Not used (returns “0” when read)
    High-breakdown-voltage drivability selection bit
    0 : Strong drivability
    1 : Weak drivability
    b7
    FLDC mode register 1
    (FLDM 1 : address 0036
    16
    )
    b0
    FLD blanking interrupt
    (at falling edge of the last digit)
    Automatic display control bit(P0, P1, P2
    0
    –P2
    3
    , P3, P8, P9, PA)
    0 : Ordinary mode
    1 : Automatic display mode
    Display start bit
    0 : Display stopped
    1 : Display in progress
    (display starts by writing “1” to this bit which is set to “0”)
    T
    disp
    control bits
    (digit time setting, at 8 MHz oscillation frequency)
    b5
    b4
    b3
    b2
    0 0 0 0 : 128
    μ
    s
    0 0 0 1 : 256
    μ
    s
    0 0 1 0 : 384
    μ
    s
    0 0 1 1 : 512
    μ
    s
    0 1 0 0 : 640
    μ
    s
    0 1 0 1 : 768
    μ
    s
    0 1 1 0 : 896
    μ
    s
    0 1 1 1 : 1024
    μ
    s
    1 0 0 0 : 1152
    μ
    s
    1 0 0 1 : 1280
    μ
    s
    1 0 1 0
    1 1 1 1
    Pl
    0
    segment/digit switch bit
    0 : Digit
    1 : Segment
    Pl
    1
    segment/digit switch bit
    0 : Digit
    1 : Segment
    b7
    FLDC mode register 2
    (FLDM 2 : address 0037
    16
    )
    b0
    Not available
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