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| 型號(hào)： | M3807 |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | Single Chip 8 Bits Microcomputer(8位單片機(jī)) |
| 中文描述： | 單芯片8位單片機(jī)（8位單片機(jī)） |
| 文件頁(yè)數(shù)： | 65/74頁(yè) |
| 文件大?。?/td> | 1182K |
| 代理商： | M3807 |
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65
3807 Group
MITSUBISHI MICROCOMPUTERS
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
SWITCHING CHARACTERISTICS
Table 20 Switching characteristics (1)
(Vcc = 4.0 to 5.5 V, Vss = 0 V, Ta = – 20 to 85
°
C, unless otherwise noted)
Min.
Typ.
Max.
Symbol
Parameter
Limits
Unit
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
t
WH
(S
CLK1
)
t
WL
(S
CLK1
)
t
d
(S
CLK1
–T
X
D)
t
v
(S
CLK1
–T
X
D)
t
r
(S
CLK1
)
t
f
(S
CLK1
)
t
WH
(S
CLK2
)
t
WL
(S
CLK2
)
t
d
(S
CLK2
–S
OUT2
)
t
v
(S
CLK2
–S
OUT2
)
t
f
(S
CLK2
)
t
r
(CMOS)
t
f
(CMOS)
Serial I/O1 clock output “H” pulse width
Serial I/O1 clock output “L” pulse width
Serial I/O1 output delay time (Note 1)
Serial I/O1 output valid time (Note 1)
Serial I/O1 clock output rising time
Serial I/O1 clock output falling time
Serial I/O2 clock output “H” pulse width
Serial I/O2 clock output “L” pulse width
Serial I/O2 output delay time (Note 2)
Serial I/O2 output valid time (Note 2)
Serial I/O2 clock output falling time
CMOS output rising time (Note 3)
CMOS output falling time (Note 3)
140
30
30
200
30
30
30
10
10
t
C
(S
CLK1
)/2–30
t
C
(S
CLK1
)/2–30
–30
t
C
(S
CLK2
)/2–160
t
C
(S
CLK2
)/2–160
0
Test conditions
Fig. 3.1.1
Fig. 3.1.1
Fig. 3.1.1
Note 1:
When the P4
5
/T
X
D P-channel output disable bit of the UART control register (bit 4 of address 001B
16
) is “0”.
2:
When the P7
1
/S
OUT2
, P7
2
/S
CLK2
P-channel output disable bit of the serial I/O2 control register1 (bit 7 of address 001D
16
) is “0”.
3:
X
OUT
pin is excluded.
Serial I/O1 clock output “H” pulse width
Serial I/O1 clock output “L” pulse width
Serial I/O1 output delay time (Note 1)
Serial I/O1 output valid time (Note 1)
Serial I/O1 clock output rising time
Serial I/O1 clock output falling time
Serial I/O2 clock output “H” pulse width
Serial I/O2 clock output “L” pulse width
Serial I/O2 output delay time (Note 2)
Serial I/O2 output valid time (Note 2)
Serial I/O2 clock output falling time
CMOS output rising time (Note 3)
CMOS output falling time (Note 3)
Min.
Typ.
Max.
Symbol
Parameter
Limits
Unit
Test conditions
t
WH
(S
CLK1
)
t
WL
(S
CLK1
)
t
d
(S
CLK1
–T
X
D)
t
v
(S
CLK1
–T
X
D)
t
r
(S
CLK1
)
t
f
(S
CLK1
)
t
WH
(S
CLK2
)
t
WL
(S
CLK2
)
t
d
(S
CLK2
–S
OUT2
)
t
v
(S
CLK2
–S
OUT2
)
t
f
(S
CLK2
)
t
r
(CMOS)
t
f
(CMOS)
Fig. 3.1.1
Fig. 3.1.1
Fig. 3.1.1
t
C
(S
CLK1
)/2–50
t
C
(S
CLK1
)/2–50
–30
t
C
(S
CLK2
)/2–240
t
C
(S
CLK2
)/2–240
0
20
20
350
50
50
400
50
50
50
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
Note 1:
When the P4
5
/T
X
D P-channel output disable bit of the UART control register (bit 4 of address 001B
16
) is “0”.
2:
When the P7
1
/S
OUT2
, P7
2
/S
CLK2
P-channel output disable bit of the serial I/O2 control register1 (bit 7 of address 001D
16
) is “0”.
3:
X
OUT
pin is excluded.
Table 21 Switching characteristics (2)
(Vcc = 2.7 to 5.5 V, Vss = 0 V, Ta = – 20 to 85
°
C, unless otherwise noted)
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