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參數(shù)資料
| 型號： | M38073M4 |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
| 中文描述： | 單芯片8位CMOS微機 |
| 文件頁數(shù)： | 38/74頁 |
| 文件大?。?/td> | 1182K |
| 代理商： | M38073M4 |
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38
MITSUBISHI MICROCOMPUTERS
3807 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
(2) Asynchronous Serial I/O (UART) Mode
Asynchronous serial I/O1 mode (UART) can be selected by clear-
ing the Serial I/O1 mode selection bit (b6) of the Serial I/O1 control
register to "0." Eight serial data transfer formats can be selected
and the transfer formats used by a transmitter and receiver must
be identical.
The transmit and receive shift registers each have a buffer (the two
buffers have the same address in memory). Since the shift register
cannot be written to or read from directly, transmit data is written to
the transmit buffer, and receive data is read from the receive buffer.
The transmit buffer can also hold the next data to be transmitted,
and the receive buffer can hold a character while the next charac-
ter is being received.
f(X
IN
)
1/4
OE
PE FE
1/16
1/16
Data bus
Receive buffer register
Address 0018
16
Receive shift register
Receive buffer full flag (RBF)
Receive interrupt request (RI)
Baud rate generator
Division ratio 1/(n+1)
Address 001C
16
ST/SP/PA generator
Transmit buffer register
Data bus
Transmit shift register
Address
0018
16
Transmit shift register shift
completion flag (TSC)
Transmit buffer empty flag (TBE)
Address
0019
16
Serial I/O1 status register
Transmit interrupt request (TI)
STdetector
SP detector
UART control register
Address 001B
16
Character length selection bit
Address 001A
16
BRG count source selection bit
Transmit interrupt source selection bit
Serial I/O1 synchronous clock
selection bit
Clock control circuit
Character length selection bit
7 bit
8 bit
(f(X
CIN
) in low-speed mode)
Serial I/O1 control register
P4
6
/S
CLK1
P4
4
/R
X
D
P4
5
/T
X
D
Fig. 35. Block diagram of UART serial I/O1
TSC=0
TBE=1
RBF=0
TBE=0
TBE=0
RBF=1
RBF=1
ST
D
0
D
1
SP
D
0
D
1
ST
SP
TBE=1
TSC=1*
ST
D
0
D
1
SP
D
0
D
1
ST
SP
Transmit or receive clock
Write-in signal to
transmit buffer register
Serial output T
X
D
Read-out signal from
receive buffer register
Serial input R
X
D
* Generated at 2nd bit in 2-stop bit mode
1 start bit
7 or 8 data bit
1 or 0 parity bit
1 or 2 stop bit
1: Error flag detection occurs at the same time that the RBF flag becomes "1" (at 1st stop bit, during reception).
2: The transmit interrupt (TI) can be selected to occur when either the TBE or TSC flag becomes "1", depending on the setting of the transmit interrupt
source selection bit (TIC) of the serial I/O1 control register.
3: The receive interrupt (RI) is set when the RBF flag becomes "1".
4: After data is written to the transmit buffer register when TSC=1, 0.5 to 1,5 cycles of the data shift cycle is necessary until changing to TSC=0.
Notes
Fig. 36. Operation of UART serial I/O1 function
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