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參數(shù)資料
| 型號： | M38073M4-A01FP |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
| 中文描述： | 單芯片8位CMOS微機(jī) |
| 文件頁數(shù)： | 37/74頁 |
| 文件大?。?/td> | 1182K |
| 代理商： | M38073M4-A01FP |
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37
3807 Group
MITSUBISHI MICROCOMPUTERS
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
Serial I/O
G
Serial I/O1
Serial I/O1 can be used as either clock synchronous or asynchro-
nous (UART) serial I/O. A dedicated timer (baud rate generator) is
also provided for baud rate generation during Serial I/O1 opera-
tion.
(1) Clock Synchronous Serial I/O Mode
Clock synchronous serial I/O1 mode can be selected by setting the
serial I/O1 mode selection bit (b6) of the serial I/O1 control register
to "1." For clock synchronous serial I/O, the transmitter and the
receiver must use the same clock for serial I/O1 operation. If an
internal clock is used, transmit/receive is started by a write signal to
the Transmit/Receive buffer register (TB/RB) (address:0018
16
).
1/4
IN
f(X
IN
)
1/4
F/F
P4
6
/S
CLK1
Serial I/O1 status register
Serial I/O 1 control register
P4
7
/S
RDY1
P4
4
/R
X
D
P4
5
/T
X
D
(f(X
CIN
) in low-speed mode)
Receive buffer register
Address 0018
16
Receive shift register
Receive buffer full flag (RBF)
Receive interrupt request (RI)
Clock control circuit
Shift clock
Serial I/O1 synchronous clock selection bit
Division ratio 1/(n+1)
Baud rate generator
Address 001C
16
BRG count source selection bit
Clock control circuit
Falling edge detector
Transmit buffer register
Data bus
Address 0018
16
Shift clock
Transmit shift register shift
completion flag (TSC)
Transmit buffer empty flag (TBE)
Address 0019
16
Transmit interrupt request (TI)
Transmit interrupt source selection bit
Data bus
Address 001A
16
Transmit shift register
D
7
D
7
D
0
D
1
D
2
D
3
D
4
D
5
D
6
D
0
D
1
D
2
D
3
D
4
D
5
D
6
RBF = 1
TSC = 1
Overrun error (OE)
detection
TBE = 0
TBE = 1
TSC = 0
Transmit/Receive shift clock
(1/2
—
1/2048 of internal
clock or external clock)
Serial output TxD
Serial input RxD
Write-in signal to transmit/receive
buffer register (address 0018
16
)
Notes 1 : The transmit interrupt (TI) can be selected to occur either when the transmit buffer has emptied (TBE=1) or after the
transmit shift operation has ended (TSC=1), by setting transmit interrupt source selection bit (TIC) of the serial I/O1
control register.
2 : If data is written to the transmit buffer register when TSC=0, the transmit clock is generated continuously and serial
data is output continuously from the TxD pin.
3 : The receive interrupt (RI) is set when the receive buffer full flag (RBF) becomes “1” .
Receive enable signal
S
RDY1
Fig. 34. Operation of clock synchronous serial I/O1 function
Fig. 33. Block diagram of clock synchronous serial I/O1
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