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參數(shù)資料
| 型號： | M38073M4-214FP |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
| 中文描述： | 單芯片8位CMOS微機(jī) |
| 文件頁數(shù)： | 47/74頁 |
| 文件大小： | 1182K |
| 代理商： | M38073M4-214FP |
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47
3807 Group
MITSUBISHI MICROCOMPUTERS
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
b0
Port P2P3 control register
(P2P3C : address 0015
16
)
b7
P3
4
clock output control bit
0: I/O port
1: Clock output
Output clock frequency selection bits
000:
φ
001: f(X
CIN
)
010: "L" fixed for output
011: "L" fixed for output
100: f(X
IN
) (f(X
CIN
) in low-speed mode)
101: f(X
IN
)/2 (f(X
CIN
)/2 in low-speed mode)
110: f(X
IN
)/4 (f(X
CIN
)/4 in low-speed mode)
111: f(X
IN
)/16 (f(X
CIN
)/16 in low-speed mode)
Not used (return "0" when read)
P2P3
2
input level selection bit
0: CMOS level input
1: TTL level input
Clock output function
The internal clock
φ
can be output from I/O port P3
4
. Control of I/O
ports and clock output function can be performed by port P2P3
control register (address 0015
16
).
(1) I/O ports or clock output function selection
The P3
4
clock output control bit (b0) of port P2P3 control register
selects the I/O port or clock output function. When clock output
function is selected, the clock is output regardless of the port P3
4
direction register settings.
Directly after bit 0 is written to, the port or clock output is switched
synchronous to a falling edge of clock frequency selected by the
output clock frequency selection bit. When memory expansion mode
or microprocessor mode is selected in CPU mode register (b1, b0),
clock output is selected on regardless of P3
4
clock output control bit
settings or port P3
4
direction register settings.
(2) Selection of output clock frequency
The output clock frequency selection bits (b3, b2, b1) of port P2P3
control register select the output clock frequency.
The output waveform when f(X
IN
) or f(X
CIN
) is selected, depends on
X
IN
or X
CIN
input waveform however; all other output waveform
settings have a duty cycle of 50%.
Note: Either high-speed, middle-speed or low-speed mode is selected by bits 7 and 6 of CPU mode register.
P3
4
port latch
P3
4
/CK
OUT
/
1/2
"110"
"111"
"100"
Output clock frequency
selection bits
X
IN
1/4
"101"
1/16
"000"
X
CIN
"001"
Main clock division ratio
selection bits (Note)
Low-speed mode
P3
4
direction register
P3
4
clock output control bit
Microprocessor mode/memory expansion mode
"010"
"011"
High-speed or
middle-speed
mode
Fig. 51. Block diagram of Clock output function
Fig. 50. Structure of Port P2P3 control register
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