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參數(shù)資料
| 型號： | M3804 |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | Single Chip 8 Bits Microcomputer(8位單片機(jī)) |
| 中文描述： | 單芯片8位單片機(jī)（8位單片機(jī)） |
| 文件頁數(shù)： | 80/135頁 |
| 文件大?。?/td> | 2055K |
| 代理商： | M3804 |
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80
3803/3804 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
[I
2
C Special Mode Control Register (S3D)]
0017
16
The I
2
C special mode control register (S3D: address 0017
16
) con-
trols special functions such as occurrence timing of reception
interrupt request and extending slave address comparison to 3
bytes.
Bit 1: ACK interrupt control bit (ACKICON)
This bit controls the timing of I
2
C interrupt request occurrence at
completion of data receiving due to master reception or slave re-
ception.
When this bit is
“
0
”
, the SCL pin low hold bit (PIN) is set to
“
0
”
in
synchronization with the falling of the last SCL clock, including the
ACK clock. The SCL pin is simultaneously held low, and the I
2
C
interrupt request occurs.
When this bit is
“
1
”
and the ACK clock bit (ACK) is
“
1
”
, the SCL pin
low hold 2 flag (PIN2) is set to
“
0
”
in synchronization with the fall-
ing of the data
’
s last SCL clock, just before the ACK clock. The
SCL pin is simultaneously held low, and the I
2
C interrupt request
occurs again. The ACK bit can be changed after the contents of
data are confirmed by using this function.
Bit 2: I
2
C slave address control bit (MSLAD)
This bit controls a slave address. When this bit is
“
0
”
, only the I
2
C
slave address register 0 (address 0FF7
16
) becomes valid as a
slave address and a read/write bit.
When this bit is
“
1
”
, all of the I
2
C slave address registers 0 to 2
(addresses 0FF7
16
to 0FF9
16
) become valid as a slave address
and a read/write bit. In this case, when an address data agrees
with any one of the I
2
C slave address registers 0 to 2, the slave
address comparison flag (AAS) is set to
“
1
”
and the I
2
C slave ad-
dress comparison flag corresponding to the agreed I
2
C slave
address registers 0 to 2 is also set to
“
1
”
.
Bit 5: SCL pin low hold 2 flag set bit (PIN2IN)
Writing
“
1
”
to this bit initializes the SCL pin low hold 2 flag (PIN2)
to
“
1
”
.
When writing
“
0
”
, nothing is generated.
Bit 6: SCL pin low hold set bit (PIN2HD)
When the SCL pin low hold bit (PIN) becomes
“
0
”
, the SCL pin is
held low. However, the SCL pin low hold bit (PIN) cannot be set to
“
0
”
by software. The SCL pin low hold set bit (PIN2HD) is used to ,
hold the SCL pin in the low state by software. When writing
“
1
”
to
this bit, the SCL pin low hold 2 flag (PIN2) becomes
“
0
”
, and the
SCL pin is held low. When writing
“
0
”
, nothing occurs.
Bit 7: STOP condition flag clear bit (SPFCL)
Writing
“
1
”
to this bit initializes the STOP condition flag (SPCF) to
“
0
”
.
When writing
“
0
”
, nothing is generated.
Fig. 76 Structure of I
2
C special mode control register
b7
b0
I
2
C
(
S
s
D
p
e
:
c
a
i
a
d
l
r
m
e
o
s
d
e
0
0
c
1
o
7
1
n
t
6
)
r
o
l
r
e
g
i
s
t
e
r
3
d
s
STOP condition flag clear bit
(Note 2)
Writing
“
1
”
to this bit initializes the STOP
condition flag to
“
0
”
.
A
C
C
O
K
N
I
MS
L
A
D
PIN2IN
S
P
F
C
L
ACK interrupt control bit
0 : At communication completion
1 : At falling of ACK clock and communication
completion
Slave address control bit
0 : One-byte slave address compare mode
1 : Three-byte slave address compare mode
Not used
(return
“
0
”
when read)
Not used
(Fix this bit to
“
0
”
.)
SCL pin low hold 2 flag set bit
(Notes 1, 2)
Writing
“
1
”
to this bit initializes the SCL pin low
hold 2 flag to
“
1
”
.
PIN2-
HD
SCL pin low hold set bit
(Notes 1, 2)
When writing
“
1
”
to this bit, the SCL pin low
hold 2 flag becomes
“
0
”
and the S
CL
pin is held
low.
N
o
t
e
s
1
2:
:
D
r
o
t
u
n
r
o
n
t
“
w
0
r
”
i
t
w
e
“
e
1
”
t
r
o
e
a
t
h
d
e
s
e
b
i
t
s
s
i
m
u
l
t
a
n
e
o
u
s
l
y
.
e
h
n
Not used
(Fix this bit to
“
0
”
.)
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