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| 型號(hào)： | M38047M8-XXXSP |
| 廠商： | Mitsubishi Electric Corporation |
| 英文描述： | SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER |
| 中文描述： | 單芯片8位CMOS微機(jī) |
| 文件頁(yè)數(shù)： | 78/135頁(yè) |
| 文件大?。?/td> | 2055K |
| 代理商： | M38047M8-XXXSP |
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78
3803/3804 Group
SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
MITSUBISHI MICROCOMPUTERS
[I
2
C START/STOP Condition Control Register
(S2D)] 0016
16
The I
2
C START/STOP condition control register (S2D: address
0016
16
) controls START/STOP condition detection.
Bits 0 to 4: START/STOP condition set bit (SSC4
–
SSC0)
SCL release time, setup time, and hold time change the detection
condition by value of the main clock divide ratio selection bit and
the oscillation frequency f(X
IN
) because these time are measured
by the internal system clock. Accordingly, set the proper value to
the START/STOP condition set bits (SSC4 to SSC0) in considered
of the system clock frequency. Refer to Table 14.
Do not set
“
00000
2
”
or an odd number to the START/STOP condi-
tion set bit (SSC4 to SSC0).
Refer to Table 15, the recommended set value to START/STOP
condition set bits (SSC4
–
SSC0) for each oscillation frequency.
Bit 5: SCL/SDA interrupt pin polarity selection bit (SIP)
An interrupt can occur when detecting the falling or rising edge of
the SCL or SDA pin. This bit selects the polarity of the SCL or SDA
pin interrupt pin.
Bit 6: SCL/SDA interrupt pin selection bit (SIS)
This bit selects the pin of which interrupt becomes valid between
the SCL pin and the SDA pin.
Note:
When changing the setting of the SCL/SDA interrupt pin polarity se-
lection bit, the SCL/SDA interrupt pin selection bit, or the I
2
C-BUS
interface enable bit ES0, the SCL/SDA interrupt request bit may be
set. When selecting the SCL/SDA interrupt source, disable the inter-
rupt before the SCL/SDA interrupt pin polarity selection bit, the SCL/
SDA interrupt pin selection bit, or the I
2
C-BUS interface enable bit
ES0 is set. Reset the request bit to
“
0
”
after setting these bits, and
enable the interrupt.
START/STOP
condition
control register
XXX11010
XXX11000
XXX00100
XXX01100
XXX01010
XXX00100
Oscillation
frequency
f(X
IN
) (MHz)
Fig. 74 Structure of I
2
C START/STOP condition control register
Note:
Do not set an odd number to the START/STOP condition set bit (SSC4 to SSC0) and
“
00000
2
”
.
Table 15 Recommended set value to START/STOP condition set bits (SSC4
–
SSC0) for each oscillation frequency
Main clock
divide ratio
System
clock
φ
(MHz)
SCL release time
(
μ
s)
Setup time
(
μ
s)
Hold time
(
μ
s)
8
8
4
2
2
8
2
2
3.5
μ
s (14 cycles)
3.25
μ
s (13 cycles)
3.0
μ
s (3 cycles)
3.5
μ
s (7 cycles)
3.0
μ
s (6 cycles)
3.0
μ
s (3 cycles)
6.75
μ
s (27 cycles)
6.25
μ
s (25 cycles)
5.0
μ
s (5 cycles)
6.5
μ
s (13 cycles)
5.5
μ
s (11 cycles)
5.0
μ
s (5 cycles)
3.25
μ
s (13 cycles)
3.0
μ
s (12 cycles)
2.0
μ
s (2 cycles)
3.0
μ
s (6 cycles)
2.5
μ
s (5 cycles)
2.0
μ
s (2 cycles)
4
1
2
1
b
7
b
0
I
2
C
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6
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