參數(shù)資料
型號： M38039M6L-XXXHP
廠商： Renesas Technology Corp.
英文描述： SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
中文描述： 單芯片8位CMOS微機
文件頁數(shù)： 25/119頁
文件大?。?/td> 1575K
代理商： M38039M6L-XXXHP
Rev.1.00
REJ03B0212-0100
Apr 2, 2007
Page 25 of 117
3803 Group (Spec.L)
INTERRUPTS
The 3803 group (Spec.L) interrupts are vector interrupts with a
fixed priority scheme, and generated by 16 sources among 21
sources: 8 external, 12 internal, and 1 software.
The interrupt sources, vector addresses
(1)
, and interrupt priority
are shown in Table 8.
Each interrupt except the BRK instruction interrupt has the
interrupt request bit and the interrupt enable bit. These bits and
the interrupt disable flag (I flag) control the acceptance of
interrupt requests. Figure 20 shows an interrupt control diagram.
An interrupt requests is accepted when all of the following
conditions are satisfied:
Interrupt disable flag.................................“0”
Interrupt request bit...................................“1”
Interrupt enable bit....................................“1”
Though the interrupt priority is determined by hardware, priority
processing can be performed by software using the above bits
and flag.
NOTES:
1. Vector addresses contain interrupt jump destination addresses.
2. Reset function in the same way as an interrupt with the highest priority.
Table 8
Interrupt vector addresses and priority
Interrupt Source
Priority
Vector
Addresses
(1)
High
FFFD
16
FFFB
16
Interrupt Request Generating
Conditions
Remarks
Low
FFFC
16
FFFA
16
Reset
(2)
INT
0
1
2
At reset
At detection of either rising or falling
edge of INT
0
input
At timer Z underflow
At detection of either rising or falling
edge of INT
1
input
At completion of serial I/O1 data
reception
At completion of serial I/O1
transmission shift or when
transmission buffer is empty
At timer X underflow
At timer Y underflow
At timer 1 underflow
At timer 2 underflow
At detection of either rising or falling
edge of CNTR
0
input
At detection of either rising or falling
edge of CNTR
1
input
At completion of serial I/O3 data
reception
At completion of serial I/O2 data
transmission or reception
At timer Z underflow
At detection of either rising or falling
edge of INT
2
input
At detection of either rising or falling
edge of INT
3
input
At detection of either rising or falling
edge of INT
4
input
At detection of either rising or falling
edge of CNTR
2
input
At completion of A/D conversion
At completion of serial I/O3
transmission shift or when
transmission buffer is empty
At BRK instruction execution
Non-maskable
External interrupt
(active edge selectable)
Timer Z
INT
1
3
FFF9
16
FFF8
16
External interrupt
(active edge selectable)
Valid when serial I/O1 is selected
Serial I/O1 reception
4
FFF7
16
FFF6
16
Serial I/O1
transmission
5
FFF5
16
FFF4
16
Valid when serial I/O1 is selected
Timer X
Timer Y
Timer 1
Timer 2
CNTR
0
6
7
8
9
10
FFF3
16
FFF1
16
FFEF
16
FFED
16
FFEB
16
FFF2
16
FFF0
16
FFEE
16
FFEC
16
FFEA
16
STP release timer underflow
External interrupt
(active edge selectable)
External interrupt
(active edge selectable)
Valid when serial I/O3 is selected
CNTR
1
11
FFE9
16
FFE8
16
Serial I/O3 reception
Serial I/O2
12
FFE7
16
FFE6
16
Valid when serial I/O2 is selected
Timer Z
INT
2
13
FFE5
16
FFE4
16
External interrupt
(active edge selectable)
External interrupt
(active edge selectable)
External interrupt
(active edge selectable)
External interrupt
(active edge selectable)
INT
3
14
FFE3
16
FFE2
16
INT
4
15
FFE1
16
FFE0
16
CNTR
2
A/D conversion
Serial I/O3
transmission
16
FFDF
16
FFDE
16
Valid when serial I/O3 is selected
BRK instruction
17
FFDD
16
FFDC
16
Non-maskable software interrupt
相關PDF資料
PDF描述
M38039M6L-XXXKP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
M38039M6L-XXXSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
M38039M6L-XXXWG 18-Mbit (512K x 36/1M x 18) Pipelined SRAM with NoBL(TM) Architecture; Architecture: NoBL, Pipeline; Density: 18 Mb; Organization: 512Kb x 36; Vcc (V): 3.1 to 3.6 V
M38039M6-XXXHP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
M38039M6-XXXKP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
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