參數(shù)資料
型號(hào): M38039M5L-XXXHP
廠商: Renesas Technology Corp.
英文描述: SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
中文描述: 單芯片8位CMOS微機(jī)
文件頁數(shù): 72/119頁
文件大?。?/td> 1575K
代理商: M38039M5L-XXXHP
Rev.1.00
REJ03B0212-0100
Apr 2, 2007
Page 72 of 117
3803 Group (Spec.L)
Fig 70. Structure of flash memory control register 2
Figure 71 shows a flowchart for setting/releasing CPU rewrite mode.
Fig 71. CPU rewrite mode set/release flowchart be sure to execute
Flash memory control register 2
(FMCR2: address : 0FE2
16
: initial value: 45
16
)
Not used
Not used (do not write “1” to this bit.)
Not used
All user block E/W enable bit
(1, 2)
0 : E/W disabled
1 : E/W enabled
Not used
b7
b0
Notes 1
: For this bit to be set to “1”, the user needs to write a “0” and then a
“1” to it in succession. For this bit to be set to “0”, write “0” only to this
bit.
2
: Effective only when the CPU rewrite mode select bit = “1”.
Table 11 State of E/W inhibition function
All user block E/W
enable bit
0
0
1
1
8 KB user block
E/W enable bit
0
1
0
1
8 KB
×
2 block
Addresses C000
16
to FFFF
16
E/W disabled
E/W disabled
E/W disabled
E/W enabled
16 KB + 24 KB block
Addresses 2000
16
to BFFF
16
E/W disabled
E/W disabled
E/W enabled
E/W enabled
Data block
Addresses 1000
16
to 1FFF
16
E/W enabled
E/W enabled
E/W enabled
E/W enabled
Start
Single-chip mode or Boot mode
Set CPU mode register
(1)
Jump to control program transferred to internal RAM
(Subsequent operations are executed by control program in
this RAM)
Transfer CPU rewrite mode control program to internal RAM
Set CPU rewrite mode select bit to “1” (by writing “0” and
Using software command executes erase, program, or other
operation
End
Write “0” to CPU rewrite mode select bit
Set all user block E/W enable bit to “1” (by writing “0” and
then “1” in succession)
“0” , at E/W enabled;
Execute read array command
(2)
Set all user block E/W enable bit to “0”
Notes 1
: Set the main clock as follows depending on the clock division ratio selection bits of CPU mode register (bits 6, 7 of address 003B
16
).
2
: Before exiting the CPU rewrite mode after completing erase or program operation, always be sure to execute the read array
command.
相關(guān)PDF資料
PDF描述
M38039M5L-XXXKP 9-Mbit (256K x 36/512K x 18) Pipelined SRAM; Architecture: Standard Sync, Pipeline SCD; Density: 9 Mb; Organization: 512Kb x 18; Vcc (V): 3.1 to 3.6 V
M38039M5L-XXXSP 9-Mbit (256K x 36/512K x 18) Flow-Through SRAM; Architecture: Standard Sync, Flow-through; Density: 9 Mb; Organization: 512Kb x 18; Vcc (V): 3.1 to 3.6 V
M38039M5L-XXXWG 9-Mbit (256K x 36/512K x 18) Flow-Through SRAM; Architecture: Standard Sync, Flow-through; Density: 9 Mb; Organization: 512Kb x 18; Vcc (V): 3.1 to 3.6 V
M38039M5-XXXHP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
M38039M5-XXXKP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
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