參數(shù)資料
型號： M38039M5-XXXKP
廠商： Renesas Technology Corp.
英文描述： SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
中文描述： 單芯片8位CMOS微機(jī)
文件頁數(shù)： 113/119頁
文件大?。?/td> 1575K
代理商： M38039M5-XXXKP
Rev.1.00
REJ03B0212-0100
Apr 2, 2007
Page 113 of 117
3803 Group (Spec.L)
NOTE:
1. When the P4
5
/T
X
D
1
P-channel output disable bit of the UART1 control register (bit 4 of address 001B
16
) is “0”.
Table 32 Switching characteristics (1)
(Mask ROM version: V
CC
= 2.0 to 5.5 V, V
SS
= 0 V, Ta =
20 to 85 °C, unless otherwise noted)
(Flash memory version: V
CC
= 2.7 to 5.5 V, V
SS
= 0 V, Ta =
20 to 85 °C, unless otherwise noted)
Symbol
Parameter
Test
conditions
Limits
Unit
Min.
Typ.
Max.
t
WH
(S
CLK1
)
t
WH
(S
CLK3
)
Serial I/O1, serial I/O3
clock output “H” pulse
width
4.5
≤
V
CC
≤
5.5 V
4.0
≤
V
CC
< 4.5 V
2.7
≤
V
CC
< 4.0 V
2.2
≤
V
CC
< 2.7 V
2.0
≤
V
CC
< 2.2 V
4.5
≤
V
CC
≤
5.5 V
4.0
≤
V
CC
< 4.5 V
2.7
≤
V
CC
< 4.0 V
2.2
≤
V
CC
< 2.7 V
2.0
≤
V
CC
< 2.2 V
4.5
≤
V
CC
≤
5.5 V
4.0
≤
V
CC
< 4.5 V
2.7
≤
V
CC
< 4.0 V
2.2
≤
V
CC
< 2.7 V
2.0
≤
V
CC
< 2.2 V
4.5
≤
V
CC
≤
5.5 V
4.0
≤
V
CC
< 4.5 V
2.7
≤
V
CC
< 4.0 V
2.2
≤
V
CC
< 2.7 V
2.0
≤
V
CC
< 2.2 V
4.5
≤
V
CC
≤
5.5 V
4.0
≤
V
CC
< 4.5 V
2.7
≤
V
CC
< 4.0 V
2.2
≤
V
CC
< 2.7 V
2.0
≤
V
CC
< 2.2 V
4.5
≤
V
CC
≤
5.5 V
4.0
≤
V
CC
< 4.5 V
2.7
≤
V
CC
< 4.0 V
2.2
≤
V
CC
< 2.7 V
2.0
≤
V
CC
< 2.2 V
4.5
≤
V
CC
≤
5.5 V
4.0
≤
V
CC
< 4.5 V
2.7
≤
V
CC
< 4.0 V
2.2
≤
V
CC
< 2.7 V
2.0
≤
V
CC
< 2.2 V
4.5
≤
V
CC
≤
5.5 V
4.0
≤
V
CC
< 4.5 V
2.7
≤
V
CC
< 4.0 V
2.2
≤
V
CC
< 2.7 V
2.0
≤
V
CC
< 2.2 V
4.5
≤
V
CC
≤
5.5 V
4.0
≤
V
CC
< 4.5 V
2.7
≤
V
CC
< 4.0 V
2.2
≤
V
CC
< 2.7 V
2.0
≤
V
CC
< 2.2 V
4.5
≤
V
CC
≤
5.5 V
4.0
≤
V
CC
< 4.5 V
2.7
≤
V
CC
< 4.0 V
2.2
≤
V
CC
< 2.7 V
2.0
≤
V
CC
< 2.2 V
Fig.100
t
C
(S
CLK1
)/2-30, t
C
(S
CLK3
)/2-30
t
C
(S
CLK1
)/2-35, t
C
(S
CLK3
)/2-35
t
C
(S
CLK1
)/2-40, t
C
(S
CLK3
)/2-40
t
C
(S
CLK1
)/2-45, t
C
(S
CLK3
)/2-45
t
C
(S
CLK1
)/2-50, t
C
(S
CLK3
)/2-50
t
C
(S
CLK1
)/2-30, t
C
(S
CLK3
)/2-30
t
C
(S
CLK1
)/2-35, t
C
(S
CLK3
)/2-35
t
C
(S
CLK1
)/2-40, t
C
(S
CLK3
)/2-40
t
C
(S
CLK1
)/2-45, t
C
(S
CLK3
)/2-45
t
C
(S
CLK1
)/2-50, t
C
(S
CLK3
)/2-50
ns
t
WL
(S
CLK1
)
t
WL
(S
CLK3
)
Serial I/O1, serial I/O3
clock output “L” pulse
width
ns
t
d
(S
CLK1
-T
x
D
1
)
t
d
(S
CLK3
-T
x
D
3
)
Serial I/O1, serial I/O3
output delay time
(1)
140
200
350
400
420
ns
t
V
(S
CLK1
-T
x
D
1
)
t
V
(S
CLK3
-T
x
D
3
)
Serial I/O1, serial I/O3
output valid time
(1)
30
30
30
30
30
ns
t
r
(S
CLK1
)
t
r
(S
CLK3
)
Serial I/O1, serial I/O3
rise time of clock
output
30
35
40
45
50
30
35
40
45
50
ns
t
f
(S
CLK1
)
t
f
(S
CLK3
)
Serial I/O1, serial I/O3
fall time of clock output
ns
t
WH
(S
CLK2
)
Serial I/O2
clock output “H” pulse
width
t
C
(S
CLK2
)/2-160
t
C
(S
CLK2
)/2-200
t
C
(S
CLK2
)/2-240
t
C
(S
CLK2
)/2-260
t
C
(S
CLK2
)/2-280
t
C
(S
CLK2
)/2-160
t
C
(S
CLK2
)/2-200
t
C
(S
CLK2
)/2-240
t
C
(S
CLK2
)/2-260
t
C
(S
CLK2
)/2-280
ns
t
WL
(S
CLK2
)
Serial I/O2
clock output “L” pulse
width
ns
t
d
(S
CLK2
-S
OUT2
) Serial I/O2
output delay time
200
250
300
350
400
ns
t
V
(S
CLK2
-S
OUT2
)
Serial I/O2
output valid time
0
0
0
0
0
ns
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