
Rev.1.00
REJ03B0212-0100
Apr 2, 2007
Page 6 of 117
3803 Group (Spec.L)
PIN DESCRIPTION
Table 2
Pin description
Pin
Name
Functions
Function except a port function
V
CC
, V
SS
Power source
Apply voltage of 1.8 V
5.5 V to V
CC
, and 0 V to V
SS
. In the flash memory version, apply
voltage of 2.7 V
5.5 V to V
CC
.
This pin controls the operation mode of the chip.
Normally connected to V
SS
.
Reference voltage input pin for A/D and D/A converters.
CNV
SS
CNV
SS
input
V
REF
Reference
voltage
Analog power
source
Reset input
Main clock input
AV
SS
Analog power source input pin for A/D and D/A converters.
Connect to V
SS
.
Reset input pin for active “L”.
Input and output pins for the clock generating circuit.
Connect a ceramic resonator or quartz-crystal oscillator between the X
IN
and X
OUT
pins to set
the oscillation frequency.
When an external clock is used, connect the clock source to the X
IN
pin and leave the X
OUT
pin
open.
8-bit CMOS I/O port.
I/O direction register allows each pin to be individually
programmed as either input or output.
CMOS compatible input level.
CMOS 3-state output structure.
Pull-up control is enabled in a bit unit.
P2
0
P2
7
(8 bits) are enabled to output large current for
LED drive.
RESET
X
IN
X
OUT
Main clock
output
P0
0
/AN
8
P0
7
/AN
15
P1
0
/INT
41
P1
1
/INT
01
P1
2
P1
7
I/O port P0
A/D converter input pin
I/O port P1
Interrupt input pin
P2
0
(LED
0
)-
P2
7
(LED
7
)
P3
0
/DA
1
P3
1
/
DA
2
P3
2
, P3
3
P3
4
/R
X
D
3
P3
5
/T
X
D
3
P3
6
/S
CLK3
P3
7
/S
RDY3
P4
0
/INT
40
/
X
COUT
P4
1
/INT
00
/
X
CIN
I/O port P2
I/O port P3
8-bit CMOS I/O port.
I/O direction register allows each pin to be individually
programmed as either input or output.
CMOS compatible input level.
P3
0
, P3
1
, P3
4
P3
7
are CMOS 3-state output structure.
P3
2
, P3
3
are N-channel open-drain output structure.
Pull-up control of P3
0
, P3
1
, P3
4
P3
7
is enabled in a bit unit.
D/A converter input pin
Serial I/O3 function pin
I/O port P4
8-bit CMOS I/O port.
I/O direction register allows each pin to be individually
programmed as either input or output.
CMOS compatible input level.
CMOS 3-state output structure.
Pull-up control is enabled in a bit unit.
Interrupt input pin
Sub-clock generating I/O pin
(resonator connected)
Interrupt input pin
P4
2
/INT
1
P4
3
/INT
2
P4
4
/R
X
D
1
P4
5
/T
X
D
1
P4
6
/S
CLK1
P4
7
/S
RDY1
/CNTR
2
P5
0
/S
IN2
P5
1
/S
OUT2
P5
2
/S
CLK2
P5
3
/S
RDY2
P5
4
/CNTR
0
P5
5
/CNTR
1
P5
6
/PWM
P5
7
/INT
3
P6
0
/AN
0
P6
7
/AN
7
Serial I/O1 function pin
Serial I/O1, timer Z function pin
Serial I/O2 function pin
I/O port P5
Timer X function pin
Timer Y function pin
PWM output pin
Interrupt input pin
A/D converter input pin
I/O port P6