參數資料
型號： M38039M4L-XXXWG
廠商： Renesas Technology Corp.
英文描述： 9-Mbit (256K x 36/512K x 18) Flow-Through SRAM; Architecture: Standard Sync, Flow-through; Density: 9 Mb; Organization: 256Kb x 36; Vcc (V): 3.1 to 3.6 V
中文描述： 單芯片8位CMOS微機
文件頁數： 103/119頁
文件大小： 1575K
代理商： M38039M4L-XXXWG
Rev.1.00
REJ03B0212-0100
Apr 2, 2007
Page 103 of 117
3803 Group (Spec.L)
Recommended operating conditions
NOTES:
1. When using A/D converter, see A/D converter recommended operating conditions.
2. The start voltage and the start time for oscillation depend on the using oscillator, oscillation circuit constant value and operating
temperature range, etc.. Particularly a high-frequency oscillator might require some notes in the low voltage operation.
3. When the oscillation frequency has a duty cycle of 50%.
4. When using the microcomputer in low-speed mode, set the sub-clock input oscillation frequency on condition that f(X
CIN
) < f(X
IN
)/3.
Table 17
Recommended operating conditions (1) (Mask ROM version)
(V
CC
= 1.8 to 5.5 V, V
SS
= 0 V, Ta = –20 to 85 °C, unless otherwise noted)
Symbol
Parameter
Conditions
Limits
Unit
Min.
2.2
2.0
2.2
2.7
4.0
4.5
1.8
2.2
2.7
4.5
Typ.
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
5.0
0
Max.
5.5
5.5
5.5
5.5
5.5
5.5
5.5
5.5
5.5
5.5
V
CC
Power source
voltage
(1)
When start oscillating
(2)
High-speed mode
f(
φ
) = f(X
IN
)/2
V
V
f(X
IN
)
≤
2.1 MHz
f(X
IN
)
≤
4.2 MHz
f(X
IN
)
≤
8.4 MHz
f(X
IN
)
≤
12.5 MHz
f(X
IN
)
≤
16.8 MHz
f(X
IN
)
≤
6.3 MHz
f(X
IN
)
≤
8.4 MHz
f(X
IN
)
≤
12.5 MHz
f(X
IN
)
≤
16.8 MHz
Middle-speed mode
f(
φ
) = f(X
IN
)/8
V
V
SS
V
IH
Power source voltage
“H” input voltage
P0
0
-P0
7
, P1
0
-P1
7
,
P2
0
-P2
7
, P3
0
, P3
1
,
P3
4
-P3
7
, P4
0
-P4
7
,
P5
0
-P5
7
, P6
0
-P6
7
“H” input voltage
P3
2
, P3
3
V
V
1.8
≤
V
CC
< 2.7 V
0.85 V
CC
V
CC
2.7
≤
V
CC
≤
5.5 V
0.8 V
CC
V
CC
V
IH
1.8
≤
V
CC
< 2.7 V
2.7
≤
V
CC
≤
5.5 V
1.8
≤
V
CC
< 2.7 V
2.7
≤
V
CC
≤
5.5 V
0.85 V
CC
0.8 V
CC
0.85 V
CC
0.8 V
CC
5.5
5.5
V
CC
V
CC
V
V
IH
“H” input voltage
RESET, X
IN
, X
CIN
,
CNV
SS
“L” input voltage
P0
0
-P0
7
, P1
0
-P1
7
,
P2
0
-P2
7
, P3
0
-P3
7
,
P4
0
-P4
7
, P5
0
-P5
7
,
P6
0
-P6
7
“L” input voltage
RESET, CNV
SS
V
V
IL
1.8
≤
V
CC
< 2.7 V
0
0.16 V
CC
V
2.7
≤
V
CC
≤
5.5 V
0
0.2 V
CC
V
IL
1.8
≤
V
CC
< 2.7 V
2.7
≤
V
CC
≤
5.5 V
1.8
≤
V
CC
≤
5.5 V
0
0
0
0.16 V
CC
0.2 V
CC
0.16 V
CC
V
V
IL
“L” input voltage
X
IN
, X
CIN
Main clock input
oscillation
frequency
(3)
V
f(X
IN
)
High-speed mode
f(
φ
) = f(X
IN
)/2
2.0
≤
V
CC
< 2.2 V
MHz
2.2
≤
V
CC
< 2.7 V
MHz
2.7
≤
V
CC
< 4.0 V
MHz
4.0
≤
V
CC
< 4.5 V
MHz
4.5
≤
V
CC
≤
5.5 V
1.8
≤
V
CC
< 2.2 V
16.8
MHz
MHz
Middle-speed mode
f(
φ
) = f(X
IN
)/8
2.2
≤
V
CC
< 2.7 V
MHz
2.7
≤
V
CC
< 4.5 V
MHz
4.5
≤
V
CC
≤
5.5 V
16.8
50
MHz
kHz
f(X
CIN
)
Sub-clock input oscillation frequency
(3, 4)
32.768
---------------------------–
2
(
)
1.05
×
---------------------------–
(
)
1.05
×
-------------------------–
)
1.05
×
---------------------------–
3
(
)
1.05
×
---------------------------–
(
)
1.05
×
3
---------------------------–
(
)
1.05
×
---------------------------+
7
(
)
1.1
×
Mask ROM Version
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