參數(shù)資料
型號： M38039M4L-XXXSP
廠商： Renesas Technology Corp.
英文描述： SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
中文描述： 單芯片8位CMOS微機(jī)
文件頁數(shù)： 10/119頁
文件大?。?/td> 1575K
代理商： M38039M4L-XXXSP
Rev.1.00
REJ03B0212-0100
Apr 2, 2007
Page 10 of 117
3803 Group (Spec.L)
Fig 8.
Register push and pop at interrupt generation and subroutine call
Interrupt request
(1)
M(S)
←
(PC
H
)
(S)
←
(S)
1
M(S)
←
(PC
L
)
(
S
)
←
(
S
)
1
.
Execute RTS
Subroutine
(S)
←
(S) + 1
(PC
L
)
←
M(S)
(S)
←
(S) + 1
(PC
H
)
←
M(S)
M(S)
←
(PC
H
)
(S)
←
(S)
1
M(S)
←
(PC
L
)
(S)
←
(S)
1
M(S)
←
(PS)
(S)
←
(S)
1
Interrupt
Service Routine
(S)
←
(S) + 1
(PS)
←
M(S)
(S)
←
(S) + 1
(PC
L
)
←
M(S)
(S)
←
(S) + 1
(PC
H
)
←
M(S)
Execute JSR
.
Execute RTI
Push Return Address
on Stack
Push Contents of
Processor
Status Register on Stack
I Flag is Set from
“0” to “1”
Fetch the Jump
Vector
POP Contents of
Processor Status Register
from Stack
POP Return
Address from Stack
POP Return
Address from
Stack
Push Return
Address
on Stack
Note 1
: Condition for acceptance of an interrupt
→
Interrupt enable flag is “1”
Interrupt disable flag is “0”
On-going Routine
Table 4
Push and pop instructions of accumulator or processor status register
Push instruction to stack
PHA
PHP
Pop instruction from stack
PLA
PLP
Accumulator
Processor status register
相關(guān)PDF資料
PDF描述
M38039M4L-XXXWG 9-Mbit (256K x 36/512K x 18) Flow-Through SRAM; Architecture: Standard Sync, Flow-through; Density: 9 Mb; Organization: 256Kb x 36; Vcc (V): 3.1 to 3.6 V
M38039M4-XXXHP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
M38039M4-XXXKP 9-Mbit (256K x 36/512K x 18) Flow-Through SRAM; Architecture: Standard Sync, Flow-through; Density: 9 Mb; Organization: 256Kb x 36; Vcc (V): 3.1 to 3.6 V
M38039M4-XXXSP SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
M38039M4-XXXWG SINGLE-CHIP 8-BIT CMOS MICROCOMPUTER
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