參數(shù)資料
型號: M38039FFL-XXXSP
廠商: Renesas Technology Corp.
英文描述: 9-Mbit (256K x 36/512K x 18) Flow-Through SRAM with NoBL(TM) Architecture; Architecture: NoBL, Flow-through; Density: 9 Mb; Organization: 256Kb x 36; Vcc (V): 3.1 to 3.6 V
中文描述: 單芯片8位CMOS微機
文件頁數(shù): 58/119頁
文件大?。?/td> 1575K
代理商: M38039FFL-XXXSP
Rev.1.00
REJ03B0212-0100
Apr 2, 2007
Page 58 of 117
3803 Group (Spec.L)
Fig 51. Structure of PWM control register
Fig 52. PWM output timing when PWM register or PWM prescaler is changed
<Notes>
The PWM starts after the PWM function enable bit is set to enable and “L” level is output from the PWM pin.
The length of this “L” level output is as follows:
(Count source selection bit = 0, where n is the value set in the prescaler)
(Count source selection bit = 1, where n is the value set in the prescaler)
b7
b0
PWM control register
(PWMCON: address 002B
16
)
PWM function enable bit
0: PWM disabled
1: PWM enabled
Count source selection bit
0: f(X
IN
) (f(X
CIN
) at low-speed mode)
1: f(X
IN
)/2 (f(X
CIN
)/2 at low-speed mode)
Not used
(return “0” when read)
PWM output
T
T
T2
B
C
PWM register
write signal
PWM prescaler
write signal
(Changes “H” term from “A” to “ B”.)
(Changes PWM period from “T” to “T2”.)
B
T
C
T2
=
When the contents of the PWM register or PWM prescaler have changed,
the PWM output will change from the next period after the change.
A
2
×
f X
IN
)
----------+
sec
f X
IN
)
-----+
sec
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相關代理商/技術參數(shù)
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